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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
de5c90ff
Commit
de5c90ff
authored
Jun 15, 2004
by
Kazuhiro Inaoka
Committed by
Nick Clifton
Jun 15, 2004
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* longlong.h: Fix macros for m32r add_ssaaaa and sub_ddmmss.
From-SVN: r83174
parent
3dd8069d
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gcc/ChangeLog
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de5c90ff
...
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@@ -12,6 +12,8 @@
(m32r_return_addr): Added for __builtin_return_address(0).
(m32r_reload_lr): Ditto.
* longlong.h: Fix macros for m32r add_ssaaaa and sub_ddmmss.
2004-06-15 Paolo Bonzini <bonzini@gnu.org>
* doc/install.texi (Prerequisites): Update libbanshee,
...
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gcc/longlong.h
View file @
de5c90ff
...
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@@ -376,17 +376,17 @@ UDItype __umulsidi3 (USItype, USItype);
#if defined (__M32R__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */
\
__asm__ ("cmp %0,%0\n\taddx %
%5,%1\n\taddx %%3,%0
" \
__asm__ ("cmp %0,%0\n\taddx %
1,%5\n\taddx %0,%3
" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "
%
0" ((USItype) (ah)), \
: "0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"
%
1" ((USItype) (al)), \
"1" ((USItype) (al)), \
"r" ((USItype) (bl)) \
: "cbit")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */
\
__asm__ ("cmp %0,%0\n\tsubx %
5,%1\n\tsubx %3,%0
" \
__asm__ ("cmp %0,%0\n\tsubx %
1,%5\n\tsubx %0,%3
" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
...
...
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