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riscv-gcc-1
Commit de4abb91 by Richard Henderson Committed by Richard Henderson
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alpha.h (MASK_FIX, TARGET_FIX): New. 

        * alpha.h (MASK_FIX, TARGET_FIX): New.
        (MASK_*): Reorganize constants.
        (CPP_AM_FIX_SPEC): New.
        (TARGET_SWITCHES): Add FIX.
        (EXTRA_SPECS): Likewise.
        (CPP_CPU_EV6_SPEC): Use FIX, not CIX.
        (SECONDARY_MEMORY_NEEDED): Likewise.
        (REGISTER_MOVE_COST): Likewise.
        * alpha.c (override_options): Add FIX support.  Always use
        ALPHA_TP_PROG for ev6.
        * alpha.md (sqrt and mov[sd]i patterns): Use FIX, not CIX.
        * alpha/elf.h (ASM_FILE_START): Look at FIX too.
        * configure.in (target_cpu_default2) [ev6]: Use FIX, not CIX.

From-SVN: r27183
parent 2ba1f15f
Showing with 124 additions and 87 deletions
gcc/ChangeLog
Wed May 26 14:18:05 1999 Richard Henderson <rth@cygnus.com>
* alpha.h (MASK_FIX, TARGET_FIX): New.
(MASK_*): Reorganize constants.
(CPP_AM_FIX_SPEC): New.
(TARGET_SWITCHES): Add FIX.
(EXTRA_SPECS): Likewise.
(CPP_CPU_EV6_SPEC): Use FIX, not CIX.
(SECONDARY_MEMORY_NEEDED): Likewise.
(REGISTER_MOVE_COST): Likewise.
* alpha.c (override_options): Add FIX support. Always use
ALPHA_TP_PROG for ev6.
* alpha.md (sqrt and mov[sd]i patterns): Use FIX, not CIX.
* alpha/elf.h (ASM_FILE_START): Look at FIX too.
* configure.in (target_cpu_default2) [ev6]: Use FIX, not CIX.
Wed May 26 09:53:05 1999 Mark Mitchell <mark@codesourcery.com> Wed May 26 09:53:05 1999 Mark Mitchell <mark@codesourcery.com>
* fold-const.c (fold): STRIP_NOPS when deciding whether or not * fold-const.c (fold): STRIP_NOPS when deciding whether or not
......
gcc/config/alpha/alpha.c
...@@ -134,49 +134,6 @@ static int alpha_does_function_need_gp ...@@ -134,49 +134,6 @@ static int alpha_does_function_need_gp
void void
override_options () override_options ()
{ {
alpha_cpu
= TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
: (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
if (alpha_cpu_string)
{
if (! strcmp (alpha_cpu_string, "ev4")
|| ! strcmp (alpha_cpu_string, "21064"))
{
alpha_cpu = PROCESSOR_EV4;
target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
}
else if (! strcmp (alpha_cpu_string, "ev5")
|| ! strcmp (alpha_cpu_string, "21164"))
{
alpha_cpu = PROCESSOR_EV5;
target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
}
else if (! strcmp (alpha_cpu_string, "ev56")
|| ! strcmp (alpha_cpu_string, "21164a"))
{
alpha_cpu = PROCESSOR_EV5;
target_flags |= MASK_BWX;
target_flags &= ~ (MASK_CIX | MASK_MAX);
}
else if (! strcmp (alpha_cpu_string, "pca56")
|| ! strcmp (alpha_cpu_string, "21164PC")
|| ! strcmp (alpha_cpu_string, "21164pc"))
{
alpha_cpu = PROCESSOR_EV5;
target_flags |= MASK_BWX | MASK_MAX;
target_flags &= ~ MASK_CIX;
}
else if (! strcmp (alpha_cpu_string, "ev6")
|| ! strcmp (alpha_cpu_string, "21264"))
{
alpha_cpu = PROCESSOR_EV6;
target_flags |= MASK_BWX | MASK_CIX | MASK_MAX;
}
else
error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
}
alpha_tp = ALPHA_TP_PROG; alpha_tp = ALPHA_TP_PROG;
alpha_fprm = ALPHA_FPRM_NORM; alpha_fprm = ALPHA_FPRM_NORM;
alpha_fptm = ALPHA_FPTM_N; alpha_fptm = ALPHA_FPTM_N;
...@@ -234,10 +191,59 @@ override_options () ...@@ -234,10 +191,59 @@ override_options ()
error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string); error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
} }
/* Do some sanity checks on the above option. */ alpha_cpu
= TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
: (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
if (alpha_cpu_string)
{
if (! strcmp (alpha_cpu_string, "ev4")
|| ! strcmp (alpha_cpu_string, "21064"))
{
alpha_cpu = PROCESSOR_EV4;
target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
}
else if (! strcmp (alpha_cpu_string, "ev5")
|| ! strcmp (alpha_cpu_string, "21164"))
{
alpha_cpu = PROCESSOR_EV5;
target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
}
else if (! strcmp (alpha_cpu_string, "ev56")
|| ! strcmp (alpha_cpu_string, "21164a"))
{
alpha_cpu = PROCESSOR_EV5;
target_flags |= MASK_BWX;
target_flags &= ~ (MASK_MAX | MASK_FIX | MASK_CIX);
}
else if (! strcmp (alpha_cpu_string, "pca56")
|| ! strcmp (alpha_cpu_string, "21164PC")
|| ! strcmp (alpha_cpu_string, "21164pc"))
{
alpha_cpu = PROCESSOR_EV5;
target_flags |= MASK_BWX | MASK_MAX;
target_flags &= ~ (MASK_FIX | MASK_CIX);
}
else if (! strcmp (alpha_cpu_string, "ev6")
|| ! strcmp (alpha_cpu_string, "21264"))
{
alpha_cpu = PROCESSOR_EV6;
target_flags |= MASK_BWX | MASK_MAX | MASK_FIX;
target_flags &= ~ (MASK_CIX);
/* Except for EV6 pass 1 (not released), we always have
precise arithmetic traps. Which means we can do
software completion without minding trap shadows. */
alpha_tp = ALPHA_TP_PROG;
}
else
error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
}
/* Do some sanity checks on the above options. */
if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI) if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
&& alpha_tp != ALPHA_TP_INSN) && (alpha_tp != ALPHA_TP_INSN || alpha_cpu == PROCESSOR_EV6))
{ {
warning ("fp software completion requires -mtrap-precision=i"); warning ("fp software completion requires -mtrap-precision=i");
alpha_tp = ALPHA_TP_INSN; alpha_tp = ALPHA_TP_INSN;
......
gcc/config/alpha/alpha.h
...@@ -95,73 +95,76 @@ extern enum alpha_fp_trap_mode alpha_fptm; ...@@ -95,73 +95,76 @@ extern enum alpha_fp_trap_mode alpha_fptm;
/* This means that floating-point support exists in the target implementation /* This means that floating-point support exists in the target implementation
of the Alpha architecture. This is usually the default. */ of the Alpha architecture. This is usually the default. */
#define MASK_FP (1 << 0)
#define MASK_FP 1
#define TARGET_FP (target_flags & MASK_FP) #define TARGET_FP (target_flags & MASK_FP)
/* This means that floating-point registers are allowed to be used. Note /* This means that floating-point registers are allowed to be used. Note
that Alpha implementations without FP operations are required to that Alpha implementations without FP operations are required to
provide the FP registers. */ provide the FP registers. */
#define MASK_FPREGS 2 #define MASK_FPREGS (1 << 1)
#define TARGET_FPREGS (target_flags & MASK_FPREGS) #define TARGET_FPREGS (target_flags & MASK_FPREGS)
/* This means that gas is used to process the assembler file. */ /* This means that gas is used to process the assembler file. */
#define MASK_GAS 4 #define MASK_GAS (1 << 2)
#define TARGET_GAS (target_flags & MASK_GAS) #define TARGET_GAS (target_flags & MASK_GAS)
/* This means that we should mark procedures as IEEE conformant. */ /* This means that we should mark procedures as IEEE conformant. */
#define MASK_IEEE_CONFORMANT 8 #define MASK_IEEE_CONFORMANT (1 << 3)
#define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT) #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
/* This means we should be IEEE-compliant except for inexact. */ /* This means we should be IEEE-compliant except for inexact. */
#define MASK_IEEE 16 #define MASK_IEEE (1 << 4)
#define TARGET_IEEE (target_flags & MASK_IEEE) #define TARGET_IEEE (target_flags & MASK_IEEE)
/* This means we should be fully IEEE-compliant. */ /* This means we should be fully IEEE-compliant. */
#define MASK_IEEE_WITH_INEXACT 32 #define MASK_IEEE_WITH_INEXACT (1 << 5)
#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT) #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
/* This means we must construct all constants rather than emitting /* This means we must construct all constants rather than emitting
them as literal data. */ them as literal data. */
#define MASK_BUILD_CONSTANTS 128 #define MASK_BUILD_CONSTANTS (1 << 6)
#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS) #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
/* This means we handle floating points in VAX F- (float) /* This means we handle floating points in VAX F- (float)
or G- (double) Format. */ or G- (double) Format. */
#define MASK_FLOAT_VAX 512 #define MASK_FLOAT_VAX (1 << 7)
#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX) #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
/* This means that the processor has byte and half word loads and stores /* This means that the processor has byte and half word loads and stores
(the BWX extension). */ (the BWX extension). */
#define MASK_BWX 1024 #define MASK_BWX (1 << 8)
#define TARGET_BWX (target_flags & MASK_BWX) #define TARGET_BWX (target_flags & MASK_BWX)
/* This means that the processor has the CIX extension. */
#define MASK_CIX 2048
#define TARGET_CIX (target_flags & MASK_CIX)
/* This means that the processor has the MAX extension. */ /* This means that the processor has the MAX extension. */
#define MASK_MAX 4096 #define MASK_MAX (1 << 9)
#define TARGET_MAX (target_flags & MASK_MAX) #define TARGET_MAX (target_flags & MASK_MAX)
/* This means that the processor has the FIX extension. */
#define MASK_FIX (1 << 10)
#define TARGET_FIX (target_flags & MASK_FIX)
/* This means that the processor has the CIX extension. */
#define MASK_CIX (1 << 11)
#define TARGET_CIX (target_flags & MASK_CIX)
/* This means that the processor is an EV5, EV56, or PCA56. This is defined /* This means that the processor is an EV5, EV56, or PCA56. This is defined
only in TARGET_CPU_DEFAULT. */ only in TARGET_CPU_DEFAULT. */
#define MASK_CPU_EV5 8192 #define MASK_CPU_EV5 (1 << 29)
/* Likewise for EV6. */ /* Likewise for EV6. */
#define MASK_CPU_EV6 16384 #define MASK_CPU_EV6 (1 << 30)
/* This means we support the .arch directive in the assembler. Only /* This means we support the .arch directive in the assembler. Only
defined in TARGET_CPU_DEFAULT. */ defined in TARGET_CPU_DEFAULT. */
#define MASK_SUPPORT_ARCH 32768 #define MASK_SUPPORT_ARCH (1 << 31)
#define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH) #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
/* These are for target os support and cannot be changed at runtime. */ /* These are for target os support and cannot be changed at runtime. */
...@@ -204,10 +207,12 @@ extern enum alpha_fp_trap_mode alpha_fptm; ...@@ -204,10 +207,12 @@ extern enum alpha_fp_trap_mode alpha_fptm;
{"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \ {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
{"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \ {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
{"no-bwx", -MASK_BWX, ""}, \ {"no-bwx", -MASK_BWX, ""}, \
{"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
{"no-cix", -MASK_CIX, ""}, \
{"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \ {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
{"no-max", -MASK_MAX, ""}, \ {"no-max", -MASK_MAX, ""}, \
{"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
{"no-fix", -MASK_FIX, ""}, \
{"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
{"no-cix", -MASK_CIX, ""}, \
{"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} } {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
#define TARGET_DEFAULT MASK_FP|MASK_FPREGS #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
...@@ -258,6 +263,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ ...@@ -258,6 +263,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
/* Corresponding to amask... */ /* Corresponding to amask... */
#define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)" #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
#define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)" #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
#define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
#define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)" #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
/* Corresponding to implver... */ /* Corresponding to implver... */
...@@ -270,7 +276,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ ...@@ -270,7 +276,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
#define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)" #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
#define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)" #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
#define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)" #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
#define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_cix)" #define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
#ifndef CPP_CPU_DEFAULT_SPEC #ifndef CPP_CPU_DEFAULT_SPEC
# if TARGET_CPU_DEFAULT & MASK_CPU_EV6 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
...@@ -320,6 +326,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ ...@@ -320,6 +326,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
#define EXTRA_SPECS \ #define EXTRA_SPECS \
{ "cpp_am_bwx", CPP_AM_BWX_SPEC }, \ { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
{ "cpp_am_max", CPP_AM_MAX_SPEC }, \ { "cpp_am_max", CPP_AM_MAX_SPEC }, \
{ "cpp_am_fix", CPP_AM_FIX_SPEC }, \
{ "cpp_am_cix", CPP_AM_CIX_SPEC }, \ { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
{ "cpp_im_ev4", CPP_IM_EV4_SPEC }, \ { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
{ "cpp_im_ev5", CPP_IM_EV5_SPEC }, \ { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
...@@ -848,10 +855,10 @@ extern int normal_memory_operand (); ...@@ -848,10 +855,10 @@ extern int normal_memory_operand ();
: NO_REGS) : NO_REGS)
/* If we are copying between general and FP registers, we need a memory /* If we are copying between general and FP registers, we need a memory
location unless the CIX extension is available. */ location unless the FIX extension is available. */
#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
(! TARGET_CIX && (CLASS1) != (CLASS2)) (! TARGET_FIX && (CLASS1) != (CLASS2))
/* Specify the mode to be used for memory when a secondary memory /* Specify the mode to be used for memory when a secondary memory
location is needed. If MODE is floating-point, use it. Otherwise, location is needed. If MODE is floating-point, use it. Otherwise,
...@@ -884,7 +891,7 @@ extern int normal_memory_operand (); ...@@ -884,7 +891,7 @@ extern int normal_memory_operand ();
#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
(((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \ (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
? 2 \ ? 2 \
: TARGET_CIX ? 3 : 4+2*alpha_memory_latency) : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
/* A C expressions returning the cost of moving data of MODE from a register to /* A C expressions returning the cost of moving data of MODE from a register to
or from memory. or from memory.
......
gcc/config/alpha/alpha.md
...@@ -1219,7 +1219,15 @@ ...@@ -1219,7 +1219,15 @@
"eqv %r1,%2,%0" "eqv %r1,%2,%0"
[(set_attr "type" "ilog")]) [(set_attr "type" "ilog")])
;; Handle the FFS insn if we support CIX. ;; Handle the FFS insn iff we support CIX.
;;
;; These didn't make it into EV6 pass 2 as planned. Instead they
;; cropped cttz/ctlz/ctpop from the old CIX and renamed it FIX for
;; "Square Root and Floating Point Convert Extension".
;;
;; I'm assured that these insns will make it into EV67 (first pass
;; due Summer 1999), presumably with a new AMASK bit, and presumably
;; will still be named CIX.
(define_expand "ffsdi2" (define_expand "ffsdi2"
[(set (match_dup 2) [(set (match_dup 2)
...@@ -1241,7 +1249,7 @@ ...@@ -1241,7 +1249,7 @@
(unspec [(match_operand:DI 1 "register_operand" "r")] 1))] (unspec [(match_operand:DI 1 "register_operand" "r")] 1))]
"TARGET_CIX" "TARGET_CIX"
"cttz %1,%0" "cttz %1,%0"
; ev6 calls all mvi and cttz/ctlz/popc class imisc, so just ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
; reuse the existing type name. ; reuse the existing type name.
[(set_attr "type" "mvi")]) [(set_attr "type" "mvi")])
...@@ -2300,7 +2308,7 @@ ...@@ -2300,7 +2308,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f") [(set (match_operand:SF 0 "register_operand" "=&f")
(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN" "TARGET_FP && TARGET_FIX && alpha_tp == ALPHA_TP_INSN"
"sqrt%,%)%& %R1,%0" "sqrt%,%)%& %R1,%0"
[(set_attr "type" "fsqrt") [(set_attr "type" "fsqrt")
(set_attr "opsize" "si") (set_attr "opsize" "si")
...@@ -2309,7 +2317,7 @@ ...@@ -2309,7 +2317,7 @@
(define_insn "sqrtsf2" (define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP && TARGET_CIX" "TARGET_FP && TARGET_FIX"
"sqrt%,%)%& %R1,%0" "sqrt%,%)%& %R1,%0"
[(set_attr "type" "fsqrt") [(set_attr "type" "fsqrt")
(set_attr "opsize" "si") (set_attr "opsize" "si")
...@@ -2318,7 +2326,7 @@ ...@@ -2318,7 +2326,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "register_operand" "=&f") [(set (match_operand:DF 0 "register_operand" "=&f")
(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN" "TARGET_FP && TARGET_FIX && alpha_tp == ALPHA_TP_INSN"
"sqrt%-%)%& %R1,%0" "sqrt%-%)%& %R1,%0"
[(set_attr "type" "fsqrt") [(set_attr "type" "fsqrt")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
...@@ -2326,7 +2334,7 @@ ...@@ -2326,7 +2334,7 @@
(define_insn "sqrtdf2" (define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
"TARGET_FP && TARGET_CIX" "TARGET_FP && TARGET_FIX"
"sqrt%-%)%& %1,%0" "sqrt%-%)%& %1,%0"
[(set_attr "type" "fsqrt") [(set_attr "type" "fsqrt")
(set_attr "trap" "yes")]) (set_attr "trap" "yes")])
...@@ -4015,7 +4023,7 @@ ...@@ -4015,7 +4023,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m") [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
(match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r"))] (match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r"))]
"! TARGET_CIX "! TARGET_FIX
&& (register_operand (operands[0], SFmode) && (register_operand (operands[0], SFmode)
|| reg_or_fp0_operand (operands[1], SFmode))" || reg_or_fp0_operand (operands[1], SFmode))"
"@ "@
...@@ -4030,7 +4038,7 @@ ...@@ -4030,7 +4038,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r") [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
(match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))] (match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
"TARGET_CIX "TARGET_FIX
&& (register_operand (operands[0], SFmode) && (register_operand (operands[0], SFmode)
|| reg_or_fp0_operand (operands[1], SFmode))" || reg_or_fp0_operand (operands[1], SFmode))"
"@ "@
...@@ -4047,7 +4055,7 @@ ...@@ -4047,7 +4055,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m") [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
(match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r"))] (match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r"))]
"! TARGET_CIX "! TARGET_FIX
&& (register_operand (operands[0], DFmode) && (register_operand (operands[0], DFmode)
|| reg_or_fp0_operand (operands[1], DFmode))" || reg_or_fp0_operand (operands[1], DFmode))"
"@ "@
...@@ -4062,7 +4070,7 @@ ...@@ -4062,7 +4070,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r") [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
(match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))] (match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
"TARGET_CIX "TARGET_FIX
&& (register_operand (operands[0], DFmode) && (register_operand (operands[0], DFmode)
|| reg_or_fp0_operand (operands[1], DFmode))" || reg_or_fp0_operand (operands[1], DFmode))"
"@ "@
...@@ -4101,7 +4109,7 @@ ...@@ -4101,7 +4109,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m") [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m")
(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f"))] (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f"))]
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_CIX "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))" || reg_or_0_operand (operands[1], SImode))"
"@ "@
...@@ -4118,7 +4126,7 @@ ...@@ -4118,7 +4126,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m,r,*f") [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m,r,*f")
(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f,f,*r"))] (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f,f,*r"))]
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_CIX "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))" || reg_or_0_operand (operands[1], SImode))"
"@ "@
...@@ -4250,7 +4258,7 @@ ...@@ -4250,7 +4258,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q") [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q")
(match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))] (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))]
"! TARGET_CIX "! TARGET_FIX
&& (register_operand (operands[0], DImode) && (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))" || reg_or_0_operand (operands[1], DImode))"
"@ "@
...@@ -4268,7 +4276,7 @@ ...@@ -4268,7 +4276,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q,r,*f") [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
(match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))] (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))]
"TARGET_CIX "TARGET_FIX
&& (register_operand (operands[0], DImode) && (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))" || reg_or_0_operand (operands[1], DImode))"
"@ "@
...@@ -5307,5 +5315,5 @@ ...@@ -5307,5 +5315,5 @@
; (match_operand:SI 1 "hard_fp_register_operand" "f")) ; (match_operand:SI 1 "hard_fp_register_operand" "f"))
; (set (match_operand:DI 2 "register_operand" "=r") ; (set (match_operand:DI 2 "register_operand" "=r")
; (sign_extend:DI (match_dup 0)))] ; (sign_extend:DI (match_dup 0)))]
; "TARGET_CIX && dead_or_set_p (insn, operands[0])" ; "TARGET_FIX && dead_or_set_p (insn, operands[0])"
; "ftois %1,%2") ; "ftois %1,%2")
gcc/config/alpha/elf.h
...@@ -58,7 +58,7 @@ do { \ ...@@ -58,7 +58,7 @@ do { \
} \ } \
fprintf (FILE, "\t.set noat\n"); \ fprintf (FILE, "\t.set noat\n"); \
fprintf (FILE, "\t.set noreorder\n"); \ fprintf (FILE, "\t.set noreorder\n"); \
if (TARGET_BWX | TARGET_MAX | TARGET_CIX) \ if (TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX) \
{ \ { \
fprintf (FILE, "\t.arch %s\n", \ fprintf (FILE, "\t.arch %s\n", \
(alpha_cpu == PROCESSOR_EV6 ? "ev6" \ (alpha_cpu == PROCESSOR_EV6 ? "ev6" \
......
gcc/configure
...@@ -5635,7 +5635,7 @@ for machine in $build $host $target; do ...@@ -5635,7 +5635,7 @@ for machine in $build $host $target; do
alpha*-*-*) alpha*-*-*)
case $machine in case $machine in
alphaev6*) alphaev6*)
target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_CIX|MASK_MAX" target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX"
;; ;;
alphapca56*) alphapca56*)
target_cpu_default2="MASK_CPU_EV5|MASK_BWX|MASK_MAX" target_cpu_default2="MASK_CPU_EV5|MASK_BWX|MASK_MAX"
......
gcc/configure.in
...@@ -3332,7 +3332,7 @@ changequote([,])dnl ...@@ -3332,7 +3332,7 @@ changequote([,])dnl
alpha*-*-*) alpha*-*-*)
case $machine in case $machine in
alphaev6*) alphaev6*)
target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_CIX|MASK_MAX" target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX"
;; ;;
alphapca56*) alphapca56*)
target_cpu_default2="MASK_CPU_EV5|MASK_BWX|MASK_MAX" target_cpu_default2="MASK_CPU_EV5|MASK_BWX|MASK_MAX"
......
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