Commit ddf80874 by David S. Miller Committed by David S. Miller

sparc.c (arith_operand, [...]): Mark mode as unused.

	* config/sparc/sparc.c (arith_operand, const64_operand,
	const64_high_operand, arith_double_4096_operand): Mark mode as
	unused.
	(create_simple_focus_bits): Remove unused arg highest_bit_set, all
	callers changed.
	(sparc_emit_set_const64): Remove unused variable i.
	(sparc_splitdi_legitimate): Likewise for addr_part.
	(ultra_code_from_mask): Likewise for mask.
	(ultra_cmove_results_ready_p): Fixup entry modulo calc.
	(ultra_flush_pipeline): Likewise.
	(ultra_fpmode_conflict_exists): Likewise, remove unused variable
	this_type, and allow loads and stores of differing FP modes as
	they do not create a conflict.
	(ultra_find_type): Initialize fpmode to SFmode, fix
	parenthesization thinkos in large conditional.
	(ultrasparc_sched_init): Mark dump and sched_verbose as unused.
	Init free_slot_mask after ultra_cur_hist is reset, not before.
	(ultrasparc_rescan_pipeline_state): Remove unused variable ucode.
	(ultrasparc_sched_reorder): Don't bzero current pipeline state,
	use ultra_flush_pipeline instead, then re-init group pointer.
	Fix statement with no effect.  If no progress made in, and no
	instructions scheduled at all, advance to new pipeline cycle else
	we get into an endless loop.
	(ultrasparc_adjust_cost): Remove previous arg.
	* config/sparc/sparc.h (ADJUST_COST): Update to reflect that.

From-SVN: r22068
parent 0078ab63
Fri Aug 28 19:00:44 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
* config/sparc/sparc.c (arith_operand, const64_operand,
const64_high_operand, arith_double_4096_operand): Mark mode as
unused.
(create_simple_focus_bits): Remove unused arg highest_bit_set, all
callers changed.
(sparc_emit_set_const64): Remove unused variable i.
(sparc_splitdi_legitimate): Likewise for addr_part.
(ultra_code_from_mask): Likewise for mask.
(ultra_cmove_results_ready_p): Fixup entry modulo calc.
(ultra_flush_pipeline): Likewise.
(ultra_fpmode_conflict_exists): Likewise, remove unused variable
this_type, and allow loads and stores of differing FP modes as
they do not create a conflict.
(ultra_find_type): Initialize fpmode to SFmode, fix
parenthesization thinkos in large conditional.
(ultrasparc_sched_init): Mark dump and sched_verbose as unused.
Init free_slot_mask after ultra_cur_hist is reset, not before.
(ultrasparc_rescan_pipeline_state): Remove unused variable ucode.
(ultrasparc_sched_reorder): Don't bzero current pipeline state,
use ultra_flush_pipeline instead, then re-init group pointer.
Fix statement with no effect. If no progress made in, and no
instructions scheduled at all, advance to new pipeline cycle else
we get into an endless loop.
(ultrasparc_adjust_cost): Remove previous arg.
* config/sparc/sparc.h (ADJUST_COST): Update to reflect that.
Fri Aug 28 13:52:35 1998 Jim Wilson <wilson@cygnus.com> Fri Aug 28 13:52:35 1998 Jim Wilson <wilson@cygnus.com>
* sparc.md (DImode, DFmode, TFmode splits): Delete self_reference * sparc.md (DImode, DFmode, TFmode splits): Delete self_reference
......
...@@ -789,7 +789,7 @@ arith_operand (op, mode) ...@@ -789,7 +789,7 @@ arith_operand (op, mode)
int int
arith_4096_operand (op, mode) arith_4096_operand (op, mode)
rtx op; rtx op;
enum machine_mode mode; enum machine_mode mode ATTRIBUTE_UNUSED;
{ {
int val; int val;
if (GET_CODE (op) != CONST_INT) if (GET_CODE (op) != CONST_INT)
...@@ -814,7 +814,7 @@ arith_add_operand (op, mode) ...@@ -814,7 +814,7 @@ arith_add_operand (op, mode)
int int
const64_operand (op, mode) const64_operand (op, mode)
rtx op; rtx op;
enum machine_mode mode; enum machine_mode mode ATTRIBUTE_UNUSED;
{ {
return ((GET_CODE (op) == CONST_INT return ((GET_CODE (op) == CONST_INT
&& SPARC_SIMM13_P (INTVAL (op))) && SPARC_SIMM13_P (INTVAL (op)))
...@@ -823,7 +823,7 @@ const64_operand (op, mode) ...@@ -823,7 +823,7 @@ const64_operand (op, mode)
&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
&& (CONST_DOUBLE_HIGH (op) == && (CONST_DOUBLE_HIGH (op) ==
((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
0xffffffff : 0))) (HOST_WIDE_INT)0xffffffff : 0)))
#endif #endif
|| GET_CODE (op) == CONSTANT_P_RTX); || GET_CODE (op) == CONSTANT_P_RTX);
} }
...@@ -832,7 +832,7 @@ const64_operand (op, mode) ...@@ -832,7 +832,7 @@ const64_operand (op, mode)
int int
const64_high_operand (op, mode) const64_high_operand (op, mode)
rtx op; rtx op;
enum machine_mode mode; enum machine_mode mode ATTRIBUTE_UNUSED;
{ {
return ((GET_CODE (op) == CONST_INT return ((GET_CODE (op) == CONST_INT
&& (INTVAL (op) & 0xfffffc00) != 0 && (INTVAL (op) & 0xfffffc00) != 0
...@@ -912,7 +912,7 @@ arith_double_operand (op, mode) ...@@ -912,7 +912,7 @@ arith_double_operand (op, mode)
int int
arith_double_4096_operand (op, mode) arith_double_4096_operand (op, mode)
rtx op; rtx op;
enum machine_mode mode; enum machine_mode mode ATTRIBUTE_UNUSED;
{ {
return (TARGET_ARCH64 && return (TARGET_ARCH64 &&
((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
...@@ -1689,12 +1689,12 @@ const64_is_2insns (high_bits, low_bits) ...@@ -1689,12 +1689,12 @@ const64_is_2insns (high_bits, low_bits)
static unsigned HOST_WIDE_INT create_simple_focus_bits static unsigned HOST_WIDE_INT create_simple_focus_bits
PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
int, int, int)); int, int));
static unsigned HOST_WIDE_INT static unsigned HOST_WIDE_INT
create_simple_focus_bits (high_bits, low_bits, highest_bit_set, lowest_bit_set, shift) create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
unsigned HOST_WIDE_INT high_bits, low_bits; unsigned HOST_WIDE_INT high_bits, low_bits;
int highest_bit_set, lowest_bit_set, shift; int lowest_bit_set, shift;
{ {
HOST_WIDE_INT hi, lo; HOST_WIDE_INT hi, lo;
...@@ -1725,7 +1725,6 @@ sparc_emit_set_const64 (op0, op1) ...@@ -1725,7 +1725,6 @@ sparc_emit_set_const64 (op0, op1)
unsigned HOST_WIDE_INT high_bits, low_bits; unsigned HOST_WIDE_INT high_bits, low_bits;
int lowest_bit_set, highest_bit_set; int lowest_bit_set, highest_bit_set;
int all_bits_between_are_set; int all_bits_between_are_set;
int i;
rtx temp; rtx temp;
/* Sanity check that we know what we are working with. */ /* Sanity check that we know what we are working with. */
...@@ -1802,7 +1801,6 @@ sparc_emit_set_const64 (op0, op1) ...@@ -1802,7 +1801,6 @@ sparc_emit_set_const64 (op0, op1)
{ {
the_const = the_const =
create_simple_focus_bits (high_bits, low_bits, create_simple_focus_bits (high_bits, low_bits,
highest_bit_set,
lowest_bit_set, 0); lowest_bit_set, 0);
} }
else if (lowest_bit_set == 0) else if (lowest_bit_set == 0)
...@@ -1839,7 +1837,7 @@ sparc_emit_set_const64 (op0, op1) ...@@ -1839,7 +1837,7 @@ sparc_emit_set_const64 (op0, op1)
{ {
unsigned HOST_WIDE_INT focus_bits = unsigned HOST_WIDE_INT focus_bits =
create_simple_focus_bits (high_bits, low_bits, create_simple_focus_bits (high_bits, low_bits,
highest_bit_set, lowest_bit_set, 10); lowest_bit_set, 10);
if (! SPARC_SETHI_P (focus_bits)) if (! SPARC_SETHI_P (focus_bits))
abort (); abort ();
...@@ -1953,7 +1951,7 @@ sparc_emit_set_const64 (op0, op1) ...@@ -1953,7 +1951,7 @@ sparc_emit_set_const64 (op0, op1)
{ {
unsigned HOST_WIDE_INT focus_bits = unsigned HOST_WIDE_INT focus_bits =
create_simple_focus_bits (high_bits, low_bits, create_simple_focus_bits (high_bits, low_bits,
highest_bit_set, lowest_bit_set, 0); lowest_bit_set, 0);
/* We can't get here in this state. */ /* We can't get here in this state. */
if (highest_bit_set < 32 if (highest_bit_set < 32
...@@ -4751,8 +4749,6 @@ sparc_splitdi_legitimate (reg, mem) ...@@ -4751,8 +4749,6 @@ sparc_splitdi_legitimate (reg, mem)
rtx reg; rtx reg;
rtx mem; rtx mem;
{ {
rtx addr_part = XEXP (mem, 0);
/* Punt if we are here by mistake. */ /* Punt if we are here by mistake. */
if (! reload_completed) if (! reload_completed)
abort (); abort ();
...@@ -6272,8 +6268,6 @@ static enum ultra_code ...@@ -6272,8 +6268,6 @@ static enum ultra_code
ultra_code_from_mask (type_mask) ultra_code_from_mask (type_mask)
int type_mask; int type_mask;
{ {
int mask;
if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
return IEU0; return IEU0;
else if (type_mask & (TMASK (TYPE_COMPARE) | else if (type_mask & (TMASK (TYPE_COMPARE) |
...@@ -6311,7 +6305,7 @@ ultra_cmove_results_ready_p (insn) ...@@ -6311,7 +6305,7 @@ ultra_cmove_results_ready_p (insn)
/* If this got dispatched in the previous /* If this got dispatched in the previous
group, the results are not ready. */ group, the results are not ready. */
entry = (ultra_cur_hist - 1) % ULTRA_NUM_HIST; entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
up = &ultra_pipe_hist[entry]; up = &ultra_pipe_hist[entry];
slot = 4; slot = 4;
while (--slot >= 0) while (--slot >= 0)
...@@ -6332,7 +6326,7 @@ ultra_fpmode_conflict_exists (fpmode) ...@@ -6332,7 +6326,7 @@ ultra_fpmode_conflict_exists (fpmode)
int hist_ent; int hist_ent;
int hist_lim; int hist_lim;
hist_ent = (ultra_cur_hist - 1) % ULTRA_NUM_HIST; hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
if (ultra_cycles_elapsed < 4) if (ultra_cycles_elapsed < 4)
hist_lim = ultra_cycles_elapsed; hist_lim = ultra_cycles_elapsed;
else else
...@@ -6346,7 +6340,6 @@ ultra_fpmode_conflict_exists (fpmode) ...@@ -6346,7 +6340,6 @@ ultra_fpmode_conflict_exists (fpmode)
{ {
rtx insn = up->group[slot]; rtx insn = up->group[slot];
enum machine_mode this_mode; enum machine_mode this_mode;
enum attr_type this_type;
rtx pat; rtx pat;
if (! insn if (! insn
...@@ -6362,16 +6355,18 @@ ultra_fpmode_conflict_exists (fpmode) ...@@ -6362,16 +6355,18 @@ ultra_fpmode_conflict_exists (fpmode)
continue; continue;
/* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
we will get a stall. */ we will get a stall. Loads and stores are independant
of these rules. */
if (GET_CODE (SET_SRC (pat)) != ABS if (GET_CODE (SET_SRC (pat)) != ABS
&& GET_CODE (SET_SRC (pat)) != NEG && GET_CODE (SET_SRC (pat)) != NEG
&& ((TMASK (get_attr_type (insn)) & && ((TMASK (get_attr_type (insn)) &
(TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT))) == 0)) TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) |
TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
return 1; return 1;
} }
hist_lim--; hist_lim--;
hist_ent = (hist_ent - 1) % ULTRA_NUM_HIST; hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1);
} }
/* No conflicts, safe to dispatch. */ /* No conflicts, safe to dispatch. */
...@@ -6407,7 +6402,7 @@ ultra_find_type (type_mask, list, start) ...@@ -6407,7 +6402,7 @@ ultra_find_type (type_mask, list, start)
if (recog_memoized (insn) >= 0 if (recog_memoized (insn) >= 0
&& (TMASK(get_attr_type (insn)) & type_mask)) && (TMASK(get_attr_type (insn)) & type_mask))
{ {
enum machine_mode fpmode; enum machine_mode fpmode = SFmode;
rtx pat = 0; rtx pat = 0;
int slot; int slot;
int check_depend = 0; int check_depend = 0;
...@@ -6451,13 +6446,13 @@ ultra_find_type (type_mask, list, start) ...@@ -6451,13 +6446,13 @@ ultra_find_type (type_mask, list, start)
&& REGNO (SUBREG_REG (SET_DEST (slot_pat))) == && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
REGNO (SUBREG_REG (SET_SRC (pat))) REGNO (SUBREG_REG (SET_SRC (pat)))
&& SUBREG_WORD (SET_DEST (slot_pat)) == && SUBREG_WORD (SET_DEST (slot_pat)) ==
SUBREG_WORD (SET_SRC (pat)))) SUBREG_WORD (SET_SRC (pat)))))
|| (check_fpmode_conflict == 1 || (check_fpmode_conflict == 1
&& GET_CODE (slot_insn) == INSN && GET_CODE (slot_insn) == INSN
&& GET_CODE (slot_pat) == SET && GET_CODE (slot_pat) == SET
&& ((GET_MODE (SET_DEST (slot_pat)) == SFmode && (GET_MODE (SET_DEST (slot_pat)) == SFmode
|| GET_MODE (SET_DEST (slot_pat)) == DFmode) || GET_MODE (SET_DEST (slot_pat)) == DFmode)
&& GET_MODE (SET_DEST (slot_pat)) != fpmode))))) && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
goto next; goto next;
} }
...@@ -6558,7 +6553,7 @@ ultra_schedule_insn (ip, ready, this, type) ...@@ -6558,7 +6553,7 @@ ultra_schedule_insn (ip, ready, this, type)
static void static void
ultra_flush_pipeline () ultra_flush_pipeline ()
{ {
ultra_cur_hist = (ultra_cur_hist + 1) % ULTRA_NUM_HIST; ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1);
ultra_cycles_elapsed += 1; ultra_cycles_elapsed += 1;
bzero ((char *) &ultra_pipe, sizeof ultra_pipe); bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
ultra_pipe.free_slot_mask = 0xf; ultra_pipe.free_slot_mask = 0xf;
...@@ -6569,14 +6564,14 @@ static int ultra_reorder_called_this_block; ...@@ -6569,14 +6564,14 @@ static int ultra_reorder_called_this_block;
/* Init our data structures for this current block. */ /* Init our data structures for this current block. */
void void
ultrasparc_sched_init (dump, sched_verbose) ultrasparc_sched_init (dump, sched_verbose)
FILE *dump; FILE *dump ATTRIBUTE_UNUSED;
int sched_verbose; int sched_verbose ATTRIBUTE_UNUSED;
{ {
bzero ((char *) &ultra_pipe_hist, sizeof ultra_pipe_hist); bzero ((char *) &ultra_pipe_hist, sizeof ultra_pipe_hist);
ultra_pipe.free_slot_mask = 0xf;
ultra_cur_hist = 0; ultra_cur_hist = 0;
ultra_cycles_elapsed = 0; ultra_cycles_elapsed = 0;
ultra_reorder_called_this_block = 0; ultra_reorder_called_this_block = 0;
ultra_pipe.free_slot_mask = 0xf;
} }
/* INSN has been scheduled, update pipeline commit state /* INSN has been scheduled, update pipeline commit state
...@@ -6621,7 +6616,6 @@ ultra_rescan_pipeline_state (ready, n_ready) ...@@ -6621,7 +6616,6 @@ ultra_rescan_pipeline_state (ready, n_ready)
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
{ {
rtx insn = up->group[i]; rtx insn = up->group[i];
enum ultra_code ucode;
int j; int j;
if (! insn) if (! insn)
...@@ -6723,8 +6717,8 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) ...@@ -6723,8 +6717,8 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
if (num_committed == 0 if (num_committed == 0
|| num_committed == up->group_size) || num_committed == up->group_size)
{ {
bzero ((char *) &ultra_pipe, sizeof ultra_pipe); ultra_flush_pipeline ();
ultra_pipe.free_slot_mask = 0xf; up = &ultra_pipe;
old_group_size = 0; old_group_size = 0;
} }
else else
...@@ -6737,7 +6731,7 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) ...@@ -6737,7 +6731,7 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
formed group so the code at the end of the loop formed group so the code at the end of the loop
knows that progress was in fact made. */ knows that progress was in fact made. */
if (up->group_size != old_group_size) if (up->group_size != old_group_size)
old_group_size == 0; old_group_size = 0;
} }
} }
...@@ -6905,9 +6899,20 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) ...@@ -6905,9 +6899,20 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
break; break;
/* Clean out the (current cycle's) pipeline state /* Clean out the (current cycle's) pipeline state
and try once more. */ and try once more. If we placed no instructions
bzero ((char *) &ultra_pipe, sizeof ultra_pipe); into the pipeline at all, it means a real hard
ultra_pipe.free_slot_mask = 0xf; conflict exists with some earlier issued instruction
so we must advance to the next cycle to clear it up. */
if (up->group_size == 0)
{
ultra_flush_pipeline ();
up = &ultra_pipe;
}
else
{
bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
ultra_pipe.free_slot_mask = 0xf;
}
} }
if (sched_verbose) if (sched_verbose)
...@@ -6938,11 +6943,10 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) ...@@ -6938,11 +6943,10 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
} }
int int
ultrasparc_adjust_cost (insn, link, dep_insn, previous, cost) ultrasparc_adjust_cost (insn, link, dep_insn, cost)
rtx insn; rtx insn;
rtx link; rtx link;
rtx dep_insn; rtx dep_insn;
rtx previous;
int cost; int cost;
{ {
enum attr_type insn_type, dep_type; enum attr_type insn_type, dep_type;
......
...@@ -2732,8 +2732,7 @@ extern struct rtx_def *legitimize_pic_address (); ...@@ -2732,8 +2732,7 @@ extern struct rtx_def *legitimize_pic_address ();
if (sparc_cpu == PROCESSOR_SUPERSPARC) \ if (sparc_cpu == PROCESSOR_SUPERSPARC) \
(COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST); \ (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST); \
else if (sparc_cpu == PROCESSOR_ULTRASPARC) \ else if (sparc_cpu == PROCESSOR_ULTRASPARC) \
(COST) = ultrasparc_adjust_cost (INSN, LINK, DEP, \ (COST) = ultrasparc_adjust_cost (INSN, LINK, DEP, COST); \
last_scheduled_insn, COST);\
else else
extern void ultrasparc_sched_reorder (); extern void ultrasparc_sched_reorder ();
......
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