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Commit dd551aa1 by Michael Meissner Committed by Michael Meissner
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constraints.md (we constraint): New constraint for 64-bit power9 vector support. 

[gcc]
2015-11-13  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/constraints.md (we constraint): New constraint for
	64-bit power9 vector support.
	(wL constraint): New constraint for the element in a vector that
	can be addressed by the MFVSRLD instruction.

	* config/rs6000/rs6000-protos.h (convert_float128_to_int): Add
	declaration.
	(convert_int_to_float128): Likewise.
	(rs6000_generate_compare): Add support for ISA 3.0 (power9)
	hardware support for IEEE 128-bit floating point.
	(rs6000_expand_float128_convert): Likewise.
	(convert_float128_to_int): Likewise.
	(convert_int_to_float128): Likewise.

	* config/rs6000/rs6000.md (UNSPEC_ROUND_TO_ODD): New unspecs for
	ISA 3.0 hardware IEEE 128-bit floating point.
	(UNSPEC_IEEE128_MOVE): Likewise.
	(UNSPEC_IEEE128_CONVERT): Likewise.
	(FMA_F): Add support for IEEE 128-bit floating point hardware
	support.
	(Ff): Add support for DImode.
	(Fv): Likewise.
	(any_fix code iterator): New and updated iterators for IEEE
	128-bit floating point hardware support.
	(any_float code iterator): Likewise.
	(s code attribute): Likewise.
	(su code attribute): Likewise.
	(az code attribute): Likewise.
	(uns code attribute): Likewise.
	(neg<mode>2, FLOAT128 iterator): Add support for IEEE 128-bit
	floating point hardware support.
	(abs<mode>2, FLOAT128 iterator): Likewise.
	(add<mode>3, IEEE128 iterator): New insns for IEEE 128-bit
	floating point hardware.
	(sub<mode>3, IEEE128 iterator): Likewise.
	(mul<mode>3, IEEE128 iterator): Likewise.
	(div<mode>3, IEEE128 iterator): Likewise.
	(copysign<mode>3, IEEE128 iterator): Likewise.
	(sqrt<mode>2, IEEE128 iterator): Likewise.
	(neg<mode>2, IEEE128 iterator): Likewise.
	(abs<mode>2, IEEE128 iterator): Likewise.
	(nabs<mode>2, IEEE128 iterator): Likewise.
	(fma<mode>4_hw, IEEE128 iterator): Likewise.
	(fms<mode>4_hw, IEEE128 iterator): Likewise.
	(nfma<mode>4_hw, IEEE128 iterator): Likewise.
	(nfms<mode>4_hw, IEEE128 iterator): Likewise.
	(extend<SFDF:mode><IEEE128:mode>2_hw): Likewise.
	(trunc<mode>df2_hw, IEEE128 iterator): Likewise.
	(trunc<mode>sf2_hw, IEEE128 iterator): Likewise.
	(fix_fixuns code attribute): Likewise.
	(float_floatuns code attribute): Likewise.
	(fix<uns>_<mode>si2_hw): Likewise.
	(fix<uns>_<mode>di2_hw): Likewise.
	(float<uns>_<mode>si2_hw): Likewise.
	(float<uns>_<mode>di2_hw): Likewise.
	(xscvqp<su>wz_<mode>): Likewise.
	(xscvqp<su>dz_<mode>): Likewise.
	(xscv<su>dqp_<mode): Likewise.
	(ieee128_mfvsrd): Likewise.
	(ieee128_mfvsrwz): Likewise.
	(ieee128_mtvsrw): Likewise.
	(ieee128_mtvsrd): Likewise.
	(trunc<mode>df2_odd): Likewise.
	(cmp<mode>_h): Likewise.
	(128-bit GPR splitters): Don't split a 128-bit move that is a
	direct move between GPR and vector registers using ISA 3.0 direct
	move instructions.
	(<u>mul<mode><dmode>3): Add support for the ISA 3.0 integer
	multiply-add instruction.

	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add ISA 3.0
	debugging.
	(rs6000_init_hard_regno_mode_ok): If ISA 3.0 and 64-bit, enable we
	constraint.  Disable the VSX<->GPR direct move helpers if we have
	the MFVSRLD and MTVSRDD instructions.
	(rs6000_secondary_reload_simple_move): Add support for doing
	vector direct moves directly without additional scratch registers
	if we have ISA 3.0 instructions.
	(rs6000_secondary_reload_direct_move): Update comments.
	(rs6000_output_move_128bit): Add support for ISA 3.0 vector
	instructions.

	* config/rs6000/vsx.md (vsx_mov<mode>): Add support for ISA 3.0
	direct move instructions.
	(vsx_movti_64bit): Likewise.
	(vsx_extract_<mode>): Likewise.

	* config/rs6000/rs6000.h (VECTOR_ELEMENT_MFVSRLD_64BIT): New
	macros for ISA 3.0 direct move instructions.
	(TARGET_DIRECT_MOVE_128): Likewise.
	(TARGET_MADDLD): Add support for the ISA 3.0 integer multiply-add
	instruction.

	* doc/md.texi (RS/6000 constraints): Document we, wF, wG, wL
	constraints.  Update wa documentation to say not to use %x<n> on
	instructions that only take Altivec registers.

[gcc/testsuite]
2015-11-13  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/float128-hw.c: New test for IEEE 128-bit
	hardware floating point support.

	* gcc.target/powerpc/direct-move-vector.c: New test for 128-bit
	vector direct move instructions.

	* gcc.target/powerpc/maddld.c: New test.

From-SVN: r230342
parent 0ac17097
Showing with 242 additions and 14 deletions
gcc/ChangeLog
2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (we constraint): New constraint for
64-bit power9 vector support.
(wL constraint): New constraint for the element in a vector that
can be addressed by the MFVSRLD instruction.
* config/rs6000/rs6000-protos.h (convert_float128_to_int): Add
declaration.
(convert_int_to_float128): Likewise.
(rs6000_generate_compare): Add support for ISA 3.0 (power9)
hardware support for IEEE 128-bit floating point.
(rs6000_expand_float128_convert): Likewise.
(convert_float128_to_int): Likewise.
(convert_int_to_float128): Likewise.
* config/rs6000/rs6000.md (UNSPEC_ROUND_TO_ODD): New unspecs for
ISA 3.0 hardware IEEE 128-bit floating point.
(UNSPEC_IEEE128_MOVE): Likewise.
(UNSPEC_IEEE128_CONVERT): Likewise.
(FMA_F): Add support for IEEE 128-bit floating point hardware
support.
(Ff): Add support for DImode.
(Fv): Likewise.
(any_fix code iterator): New and updated iterators for IEEE
128-bit floating point hardware support.
(any_float code iterator): Likewise.
(s code attribute): Likewise.
(su code attribute): Likewise.
(az code attribute): Likewise.
(uns code attribute): Likewise.
(neg<mode>2, FLOAT128 iterator): Add support for IEEE 128-bit
floating point hardware support.
(abs<mode>2, FLOAT128 iterator): Likewise.
(add<mode>3, IEEE128 iterator): New insns for IEEE 128-bit
floating point hardware.
(sub<mode>3, IEEE128 iterator): Likewise.
(mul<mode>3, IEEE128 iterator): Likewise.
(div<mode>3, IEEE128 iterator): Likewise.
(copysign<mode>3, IEEE128 iterator): Likewise.
(sqrt<mode>2, IEEE128 iterator): Likewise.
(neg<mode>2, IEEE128 iterator): Likewise.
(abs<mode>2, IEEE128 iterator): Likewise.
(nabs<mode>2, IEEE128 iterator): Likewise.
(fma<mode>4_hw, IEEE128 iterator): Likewise.
(fms<mode>4_hw, IEEE128 iterator): Likewise.
(nfma<mode>4_hw, IEEE128 iterator): Likewise.
(nfms<mode>4_hw, IEEE128 iterator): Likewise.
(extend<SFDF:mode><IEEE128:mode>2_hw): Likewise.
(trunc<mode>df2_hw, IEEE128 iterator): Likewise.
(trunc<mode>sf2_hw, IEEE128 iterator): Likewise.
(fix_fixuns code attribute): Likewise.
(float_floatuns code attribute): Likewise.
(fix<uns>_<mode>si2_hw): Likewise.
(fix<uns>_<mode>di2_hw): Likewise.
(float<uns>_<mode>si2_hw): Likewise.
(float<uns>_<mode>di2_hw): Likewise.
(xscvqp<su>wz_<mode>): Likewise.
(xscvqp<su>dz_<mode>): Likewise.
(xscv<su>dqp_<mode): Likewise.
(ieee128_mfvsrd): Likewise.
(ieee128_mfvsrwz): Likewise.
(ieee128_mtvsrw): Likewise.
(ieee128_mtvsrd): Likewise.
(trunc<mode>df2_odd): Likewise.
(cmp<mode>_h): Likewise.
(128-bit GPR splitters): Don't split a 128-bit move that is a
direct move between GPR and vector registers using ISA 3.0 direct
move instructions.
(<u>mul<mode><dmode>3): Add support for the ISA 3.0 integer
multiply-add instruction.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add ISA 3.0
debugging.
(rs6000_init_hard_regno_mode_ok): If ISA 3.0 and 64-bit, enable we
constraint. Disable the VSX<->GPR direct move helpers if we have
the MFVSRLD and MTVSRDD instructions.
(rs6000_secondary_reload_simple_move): Add support for doing
vector direct moves directly without additional scratch registers
if we have ISA 3.0 instructions.
(rs6000_secondary_reload_direct_move): Update comments.
(rs6000_output_move_128bit): Add support for ISA 3.0 vector
instructions.
* config/rs6000/vsx.md (vsx_mov<mode>): Add support for ISA 3.0
direct move instructions.
(vsx_movti_64bit): Likewise.
(vsx_extract_<mode>): Likewise.
* config/rs6000/rs6000.h (VECTOR_ELEMENT_MFVSRLD_64BIT): New
macros for ISA 3.0 direct move instructions.
(TARGET_DIRECT_MOVE_128): Likewise.
(TARGET_MADDLD): Add support for the ISA 3.0 integer multiply-add
instruction.
* doc/md.texi (RS/6000 constraints): Document we, wF, wG, wL
constraints. Update wa documentation to say not to use %x<n> on
instructions that only take Altivec registers.
2015-11-13 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS): Add gcc-rich-location.o.
gcc/config/rs6000/constraints.md
......@@ -64,7 +64,8 @@
(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
"VSX vector register to hold vector double data or NO_REGS.")
;; we is not currently used
(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
"VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
"VSX vector register to hold vector float data or NO_REGS.")
......@@ -147,6 +148,12 @@
"Memory operand suitable for TOC fusion memory references"
(match_operand 0 "toc_fusion_mem_wrapped"))
(define_constraint "wL"
"Int constant that is the element number mfvsrld accesses in a vector."
(and (match_code "const_int")
(and (match_test "TARGET_DIRECT_MOVE_128")
(match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))))
;; Lq/stq validates the address for load/store quad
(define_memory_constraint "wQ"
"Memory operand suitable for the load/store quad instructions"
......
gcc/config/rs6000/rs6000-protos.h
......@@ -55,6 +55,8 @@ extern const char *rs6000_output_move_128bit (rtx *);
extern bool rs6000_move_128bit_ok_p (rtx []);
extern bool rs6000_split_128bit_ok_p (rtx []);
extern void rs6000_expand_float128_convert (rtx, rtx, bool);
extern void convert_float128_to_int (rtx *, enum rtx_code);
extern void convert_int_to_float128 (rtx *, enum rtx_code);
extern void rs6000_expand_vector_init (rtx, rtx);
extern void paired_expand_vector_init (rtx, rtx);
extern void rs6000_expand_vector_set (rtx, rtx, int);
......
gcc/config/rs6000/rs6000.h
......@@ -516,6 +516,10 @@ extern int rs6000_vector_align[];
with scalar instructions. */
#define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
/* Element number of the 64-bit value in a 128-bit vector that can be accessed
with the ISA 3.0 MFVSRLD instructions. */
#define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
/* Alignment options for fields in structures for sub-targets following
AIX-like ABI.
ALIGN_POWER word-aligns FP doubles (default AIX ABI).
......@@ -567,10 +571,13 @@ extern int rs6000_vector_align[];
#define TARGET_FCTIWUZ TARGET_POPCNTD
#define TARGET_CTZ TARGET_MODULO
#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
&& TARGET_POWERPC64)
/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
in power7, so conditionalize them on p8 features. TImode syncs need quad
......@@ -1517,6 +1524,7 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_v, /* Altivec registers */
RS6000_CONSTRAINT_wa, /* Any VSX register */
RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
......
gcc/config/rs6000/vsx.md
......@@ -760,31 +760,31 @@
"")
(define_insn "*vsx_mov<mode>"
[(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?<VSa>,?<VSa>,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ, v")
(match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,<VSa>,Z,<VSa>,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
[(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?<VSa>,?<VSa>,r,we,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ,v")
(match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,<VSa>,Z,<VSa>,we,b,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
"VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
{
return rs6000_output_move_128bit (operands);
}
[(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,load,store,store,load, *,vecsimple,vecsimple,*, *,vecstore,vecload")
(set_attr "length" "4,4,4,4,4,4,12,12,12,12,16,4,4,*,16,4,4")])
[(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,mffgpr,mftgpr,load,store,store,load, *,vecsimple,vecsimple,*, *,vecstore,vecload")
(set_attr "length" "4,4,4,4,4,4,8,4,12,12,12,12,16,4,4,*,16,4,4")])
;; Unlike other VSX moves, allow the GPRs even for reloading, since a normal
;; use of TImode is for unions. However for plain data movement, slightly
;; favor the vector loads
(define_insn "*vsx_movti_64bit"
[(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v,v,wZ,wQ,&r,Y,r,r,?r")
(match_operand:TI 1 "input_operand" "wa,Z,wa,O,W,wZ,v,r,wQ,r,Y,r,n"))]
[(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,r,we,v,v,wZ,wQ,&r,Y,r,r,?r")
(match_operand:TI 1 "input_operand" "wa,Z,wa,O,we,b,W,wZ,v,r,wQ,r,Y,r,n"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)
&& (register_operand (operands[0], TImode)
|| register_operand (operands[1], TImode))"
{
return rs6000_output_move_128bit (operands);
}
[(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,load,store,load,*,*")
(set_attr "length" "4,4,4,4,16,4,4,8,8,8,8,8,8")])
[(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,mffgpr,mftgpr,vecsimple,vecstore,vecload,store,load,store,load,*,*")
(set_attr "length" "4,4,4,4,8,4,16,4,4,8,8,8,8,8,8")])
(define_insn "*vsx_movti_32bit"
[(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,Q,Y,????r,????r,????r,r")
......@@ -1909,11 +1909,11 @@
;; Optimize cases were we can do a simple or direct move.
;; Or see if we can avoid doing the move at all
(define_insn "*vsx_extract_<mode>_internal1"
[(set (match_operand:<VS_scalar> 0 "register_operand" "=d,<VS_64reg>,r")
[(set (match_operand:<VS_scalar> 0 "register_operand" "=d,<VS_64reg>,r,r")
(vec_select:<VS_scalar>
(match_operand:VSX_D 1 "register_operand" "d,<VS_64reg>,<VS_64dm>")
(match_operand:VSX_D 1 "register_operand" "d,<VS_64reg>,<VS_64dm>,<VS_64dm>")
(parallel
[(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))]
[(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD,wL")])))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
{
int op0_regno = REGNO (operands[0]);
......@@ -1923,14 +1923,16 @@
return "nop";
if (INT_REGNO_P (op0_regno))
return "mfvsrd %0,%x1";
return ((INTVAL (operands[2]) == VECTOR_ELEMENT_MFVSRLD_64BIT)
? "mfvsrdl %0,%x1"
: "mfvsrd %0,%x1");
if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno))
return "fmr %0,%1";
return "xxlor %x0,%x1,%x1";
}
[(set_attr "type" "fp,vecsimple,mftgpr")
[(set_attr "type" "fp,vecsimple,mftgpr,mftgpr")
(set_attr "length" "4")])
(define_insn "*vsx_extract_<mode>_internal2"
......
gcc/doc/md.texi
......@@ -3121,9 +3121,28 @@ asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
is not correct.
If an instruction only takes Altivec registers, you do not want to use
@code{%x<n>}.
@smallexample
asm ("xsaddqp %0,%1,%2" : "=v" (v1) : "v" (v2), "v" (v3));
@end smallexample
is correct because the @code{xsaddqp} instruction only takes Altivec
registers, while:
@smallexample
asm ("xsaddqp %x0,%x1,%x2" : "=v" (v1) : "v" (v2), "v" (v3));
@end smallexample
is incorrect.
@item wd
VSX vector register to hold vector double data or NO_REGS.
@item we
VSX register if the -mpower9-vector -m64 options were used or NO_REGS.
@item wf
VSX vector register to hold vector float data or NO_REGS.
......@@ -3187,6 +3206,16 @@ Floating point register if the LFIWZX instruction is enabled or NO_REGS.
@item wD
Int constant that is the element number of the 64-bit scalar in a vector.
@item wF
Memory operand suitable for power9 fusion load/stores.
@item wG
Memory operand suitable for TOC fusion memory references.
@item wL
Int constant that is the element number that the MFVSRLD instruction
targets.
@item wQ
A memory address that will work with the @code{lq} and @code{stq}
instructions.
......
gcc/testsuite/ChangeLog
2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/float128-hw.c: New test for IEEE 128-bit
hardware floating point support.
* gcc.target/powerpc/direct-move-vector.c: New test for 128-bit
vector direct move instructions.
* gcc.target/powerpc/maddld.c: New test.
2015-11-13 Uros Bizjak <ubizjak@gmail.com>
* gcc.dg/pr68306.c (dg-additional-options): Add i?86-*-* target.
......
gcc/testsuite/gcc.target/powerpc/direct-move-vector.c 0 → 100644
/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -O2" } */
/* Check code generation for direct move for long types. */
void
test (vector double *p)
{
vector double v1 = *p;
vector double v2;
vector double v3;
vector double v4;
/* Force memory -> FPR load. */
__asm__ (" # reg %x0" : "+d" (v1));
/* force VSX -> GPR direct move. */
v2 = v1;
__asm__ (" # reg %0" : "+r" (v2));
/* Force GPR -> Altivec direct move. */
v3 = v2;
__asm__ (" # reg %x0" : "+v" (v3));
*p = v3;
}
/* { dg-final { scan-assembler "mfvsrd" } } */
/* { dg-final { scan-assembler "mfvsrld" } } */
/* { dg-final { scan-assembler "mtvsrdd" } } */
gcc/testsuite/gcc.target/powerpc/float128-hw.c 0 → 100644
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_float128_hw_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -O2" } */
__float128 f128_add (__float128 a, __float128 b) { return a+b; }
__float128 f128_sub (__float128 a, __float128 b) { return a-b; }
__float128 f128_mul (__float128 a, __float128 b) { return a*b; }
__float128 f128_div (__float128 a, __float128 b) { return a/b; }
__float128 f128_fma (__float128 a, __float128 b, __float128 c) { return (a*b)+c; }
long f128_cmove (__float128 a, __float128 b, long c, long d) { return (a == b) ? c : d; }
/* { dg-final { scan-assembler "xsaddqp" } } */
/* { dg-final { scan-assembler "xssubqp" } } */
/* { dg-final { scan-assembler "xsmulqp" } } */
/* { dg-final { scan-assembler "xsdivqp" } } */
/* { dg-final { scan-assembler "xsmaddqp" } } */
/* { dg-final { scan-assembler "xscmpuqp" } } */
gcc/testsuite/gcc.target/powerpc/maddld.c 0 → 100644
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9modulo_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -O2" } */
long
s_madd (long a, long b, long c)
{
return (a * b) + c;
}
unsigned long
u_madd (unsigned long a, unsigned long b, unsigned long c)
{
return (a * b) + c;
}
/* { dg-final { scan-assembler-times "maddld " 2 } } */
/* { dg-final { scan-assembler-not "mulld " } } */
/* { dg-final { scan-assembler-not "add " } } */
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