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Commit dd1bdce4 by Venkataramanan Kumar Committed by Venkataramanan Kumar
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re PR target/66049 (Few AArch64 extend and add with shift tests generates sub… 

re PR target/66049 (Few AArch64 extend and add with shift tests generates sub optimal code with trunk gcc 6.0.)

2015-05-26  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>

        PR target/66049
        * config/aarch64/aarch64.md
        (*adds_shift_imm_<mode>):  New pattern.
        (*subs_shift_imm_<mode>):  Likewise.
        (*adds_<optab><ALLX:mode>_shift_<GPI:mode>):  Likewise.
        (*subs_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
        (*add_uxt<mode>_shift2): Likewise.
        (*add_uxtsi_shift2_uxtw): Likewise.
        (*sub_uxt<mode>_shift2): Likewise.
        (*sub_uxtsi_shift2_uxtw): Likewise.

From-SVN: r223703
parent efac9d45
Showing with 145 additions and 0 deletions
gcc/ChangeLog
2015-05-26 Venkataramanan Kumar <venkataramanan.kumar@amd.com>
PR target/66049
* config/aarch64/aarch64.md
(*adds_shift_imm_<mode>): New pattern.
(*subs_shift_imm_<mode>): Likewise.
(*adds_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*subs_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*add_uxt<mode>_shift2): Likewise.
(*add_uxtsi_shift2_uxtw): Likewise.
(*sub_uxt<mode>_shift2): Likewise.
(*sub_uxtsi_shift2_uxtw): Likewise.
2015-05-26 David Edelsohn <dje.gcc@gmail.com>
* config/rs6000/constraints.md (Y, U): Use match_test.
......
gcc/config/aarch64/aarch64.md
......@@ -1539,6 +1539,38 @@
[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
)
(define_insn "*adds_shift_imm_<mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI (ASHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
(match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))
(match_dup 3)))]
""
"adds\\t%<w>0, %<w>3, %<w>1, <shift> %2"
[(set_attr "type" "alus_shift_imm")]
)
(define_insn "*subs_shift_imm_<mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(minus:GPI (match_operand:GPI 1 "register_operand" "r")
(ASHIFT:GPI
(match_operand:GPI 2 "register_operand" "r")
(match_operand:QI 3 "aarch64_shift_imm_<mode>" "n")))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_dup 1)
(ASHIFT:GPI (match_dup 2) (match_dup 3))))]
""
"subs\\t%<w>0, %<w>1, %<w>2, <shift> %3"
[(set_attr "type" "alus_shift_imm")]
)
(define_insn "*adds_mul_imm_<mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
......@@ -1599,6 +1631,42 @@
[(set_attr "type" "alus_ext")]
)
(define_insn "*adds_<optab><ALLX:mode>_shift_<GPI:mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI (ashift:GPI
(ANY_EXTEND:GPI
(match_operand:ALLX 1 "register_operand" "r"))
(match_operand 2 "aarch64_imm3" "Ui3"))
(match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=rk")
(plus:GPI (ashift:GPI (ANY_EXTEND:GPI (match_dup 1))
(match_dup 2))
(match_dup 3)))]
""
"adds\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
[(set_attr "type" "alus_ext")]
)
(define_insn "*subs_<optab><ALLX:mode>_shift_<GPI:mode>"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(minus:GPI (match_operand:GPI 1 "register_operand" "r")
(ashift:GPI
(ANY_EXTEND:GPI
(match_operand:ALLX 2 "register_operand" "r"))
(match_operand 3 "aarch64_imm3" "Ui3")))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=rk")
(minus:GPI (match_dup 1)
(ashift:GPI (ANY_EXTEND:GPI (match_dup 2))
(match_dup 3))))]
""
"subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
[(set_attr "type" "alus_ext")]
)
(define_insn "*adds_<optab><mode>_multp2"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
......@@ -1894,6 +1962,38 @@
[(set_attr "type" "adc_reg")]
)
(define_insn "*add_uxt<mode>_shift2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(plus:GPI (and:GPI
(ashift:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "aarch64_imm3" "Ui3"))
(match_operand 3 "const_int_operand" "n"))
(match_operand:GPI 4 "register_operand" "r")))]
"aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0"
"*
operands[3] = GEN_INT (aarch64_uxt_size (INTVAL(operands[2]),
INTVAL (operands[3])));
return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
[(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
(define_insn "*add_uxtsi_shift2_uxtw"
[(set (match_operand:DI 0 "register_operand" "=rk")
(zero_extend:DI
(plus:SI (and:SI
(ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 2 "aarch64_imm3" "Ui3"))
(match_operand 3 "const_int_operand" "n"))
(match_operand:SI 4 "register_operand" "r"))))]
"aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0"
"*
operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]),
INTVAL (operands[3])));
return \"add\t%w0, %w4, %w1, uxt%e3 %2\";"
[(set_attr "type" "alu_ext")]
)
(define_insn "*add_uxt<mode>_multp2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(plus:GPI (and:GPI
......@@ -2150,6 +2250,38 @@
[(set_attr "type" "adc_reg")]
)
(define_insn "*sub_uxt<mode>_shift2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(minus:GPI (match_operand:GPI 4 "register_operand" "rk")
(and:GPI
(ashift:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "aarch64_imm3" "Ui3"))
(match_operand 3 "const_int_operand" "n"))))]
"aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0"
"*
operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]),
INTVAL (operands[3])));
return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
[(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
(define_insn "*sub_uxtsi_shift2_uxtw"
[(set (match_operand:DI 0 "register_operand" "=rk")
(zero_extend:DI
(minus:SI (match_operand:SI 4 "register_operand" "rk")
(and:SI
(ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 2 "aarch64_imm3" "Ui3"))
(match_operand 3 "const_int_operand" "n")))))]
"aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0"
"*
operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]),
INTVAL (operands[3])));
return \"sub\t%w0, %w4, %w1, uxt%e3 %2\";"
[(set_attr "type" "alu_ext")]
)
(define_insn "*sub_uxt<mode>_multp2"
[(set (match_operand:GPI 0 "register_operand" "=rk")
(minus:GPI (match_operand:GPI 4 "register_operand" "rk")
......
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