Commit dd01cd0c by Andreas Krebbel Committed by Andreas Krebbel

S/390: Add missing constraints in builtin patterns

gcc/ChangeLog:

2017-03-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/vx-builtins.md ("vfee<mode>", "vfeez<mode>")
	("vfenez<mode>"): Add missing constraints.

From-SVN: r245987
parent 89262ec6
2017-03-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/vx-builtins.md ("vfee<mode>", "vfeez<mode>")
("vfenez<mode>"): Add missing constraints.
2017-03-08 Martin Sebor <msebor@redhat.com> 2017-03-08 Martin Sebor <msebor@redhat.com>
PR target/79928 PR target/79928
......
...@@ -1351,9 +1351,9 @@ ...@@ -1351,9 +1351,9 @@
; vfeeb, vfeeh, vfeef ; vfeeb, vfeeh, vfeef
(define_insn "vfee<mode>" (define_insn "vfee<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "") [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
(match_operand:VI_HW_QHS 2 "register_operand" "") (match_operand:VI_HW_QHS 2 "register_operand" "v")
(const_int 0)] (const_int 0)]
UNSPEC_VEC_VFEE))] UNSPEC_VEC_VFEE))]
"TARGET_VX" "TARGET_VX"
...@@ -1362,9 +1362,9 @@ ...@@ -1362,9 +1362,9 @@
; vfeezb, vfeezh, vfeezf ; vfeezb, vfeezh, vfeezf
(define_insn "vfeez<mode>" (define_insn "vfeez<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "") [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
(match_operand:VI_HW_QHS 2 "register_operand" "") (match_operand:VI_HW_QHS 2 "register_operand" "v")
(const_int VSTRING_FLAG_ZS)] (const_int VSTRING_FLAG_ZS)]
UNSPEC_VEC_VFEE))] UNSPEC_VEC_VFEE))]
"TARGET_VX" "TARGET_VX"
...@@ -1423,9 +1423,9 @@ ...@@ -1423,9 +1423,9 @@
; vfenezb, vfenezh, vfenezf ; vfenezb, vfenezh, vfenezf
(define_insn "vfenez<mode>" (define_insn "vfenez<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "") [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "") (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
(match_operand:VI_HW_QHS 2 "register_operand" "") (match_operand:VI_HW_QHS 2 "register_operand" "v")
(const_int VSTRING_FLAG_ZS)] (const_int VSTRING_FLAG_ZS)]
UNSPEC_VEC_VFENE))] UNSPEC_VEC_VFENE))]
"TARGET_VX" "TARGET_VX"
......
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