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riscv-gcc-1
Commit dcffbade by Steve Ellcey Committed by Steve Ellcey
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ia64.h (MASK_INLINE_DIV_LAT): Remove. 

	* config/ia64/ia64.h (MASK_INLINE_DIV_LAT): Remove.
	(MASK_INLINE_DIV_THR): Remove.
	(TARGET_INLINE_DIV_LAT): Remove.
	(TARGET_INLINE_DIV_THR): Remove.
	(TARGET_INLINE_DIV): Remove.
	(MASK_INLINE_FLOAT_DIV_LAT): New macro.
	(MASK_INLINE_FLOAT_DIV_THR): New macro.
	(MASK_INLINE_INT_DIV_LAT): New macro.
	(MASK_INLINE_INT_DIV_THR): New macro.
	(TARGET_INLINE_FLOAT_DIV_LAT): New macro.
	(TARGET_INLINE_FLOAT_DIV_THR): New macro.
	(TARGET_INLINE_INT_DIV_LAT): New macro.
	(TARGET_INLINE_INT_DIV_THR): New macro.
	(TARGET_INLINE_FLOAT_DIV): New macro.
	(TARGET_INLINE_INT_DIV): New macro.
	* config/ia64/ia64.md (divsi3): Change to use new macros.
	(modsi3): Ditto.
	(udivsi3): Ditto.
	(umodsi3): Ditto.
	(divsi3_internal): Ditto.
	(divdi3): Ditto.
	(moddi3): Ditto.
	(udivdi3): Ditto.
	(umoddi3): Ditto.
	(divdi3_internal_lat): Ditto.
	(divdi3_internal_thr): Ditto.
	(divsf3): Ditto.
	(divsf3_internal_lat): Ditto.
	(divsf3_internal_thr): Ditto.
	(divdf3): Ditto.
	(divdf3_internal_lat): Ditto.
	(divdf3_internal_thr): Ditto.
	(divtf3): Ditto.
	(divtf3_internal_lat): Ditto.
	(divtf3_internal_thr): Ditto.
	* config/ia64/ia64.c (ia64_override_options): Change
	to check new macros for conflicts in settings.
	* doc/invoke.texi (-minline-divide-min-latency): Remove.
	(-minline-divide-max-throughput): Remove.
	(-minline-float-divide-min-latency): New.
	(-minline-float-divide-max-throughput): New.
	(-minline-int-divide-min-latency): New.
	(-minline-int-divide-max-throughput): New.

From-SVN: r58727
parent 0e75523e
Showing with 127 additions and 47 deletions
gcc/ChangeLog
2002-11-01 Steve Ellcey <sje@cup.hp.com>
* config/ia64/ia64.h (MASK_INLINE_DIV_LAT): Remove.
(MASK_INLINE_DIV_THR): Remove.
(TARGET_INLINE_DIV_LAT): Remove.
(TARGET_INLINE_DIV_THR): Remove.
(TARGET_INLINE_DIV): Remove.
(MASK_INLINE_FLOAT_DIV_LAT): New macro.
(MASK_INLINE_FLOAT_DIV_THR): New macro.
(MASK_INLINE_INT_DIV_LAT): New macro.
(MASK_INLINE_INT_DIV_THR): New macro.
(TARGET_INLINE_FLOAT_DIV_LAT): New macro.
(TARGET_INLINE_FLOAT_DIV_THR): New macro.
(TARGET_INLINE_INT_DIV_LAT): New macro.
(TARGET_INLINE_INT_DIV_THR): New macro.
(TARGET_INLINE_FLOAT_DIV): New macro.
(TARGET_INLINE_INT_DIV): New macro.
* config/ia64/ia64.md (divsi3): Change to use new macros.
(modsi3): Ditto.
(udivsi3): Ditto.
(umodsi3): Ditto.
(divsi3_internal): Ditto.
(divdi3): Ditto.
(moddi3): Ditto.
(udivdi3): Ditto.
(umoddi3): Ditto.
(divdi3_internal_lat): Ditto.
(divdi3_internal_thr): Ditto.
(divsf3): Ditto.
(divsf3_internal_lat): Ditto.
(divsf3_internal_thr): Ditto.
(divdf3): Ditto.
(divdf3_internal_lat): Ditto.
(divdf3_internal_thr): Ditto.
(divtf3): Ditto.
(divtf3_internal_lat): Ditto.
(divtf3_internal_thr): Ditto.
* config/ia64/ia64.c (ia64_override_options): Change
to check new macros for conflicts in settings.
* doc/invoke.texi (-minline-divide-min-latency): Remove.
(-minline-divide-max-throughput): Remove.
(-minline-float-divide-min-latency): New.
(-minline-float-divide-max-throughput): New.
(-minline-int-divide-min-latency): New.
(-minline-int-divide-max-throughput): New.
2002-11-01 Richard Earnshaw (rearnsha@arm.com)
PR target/7856
......
gcc/config/ia64/ia64.c
......@@ -4169,10 +4169,16 @@ ia64_override_options ()
if (TARGET_AUTO_PIC)
target_flags |= MASK_CONST_GP;
if (TARGET_INLINE_DIV_LAT && TARGET_INLINE_DIV_THR)
if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
{
warning ("cannot optimize division for both latency and throughput");
target_flags &= ~MASK_INLINE_DIV_THR;
warning ("cannot optimize floating point division for both latency and throughput");
target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
}
if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
{
warning ("cannot optimize integer division for both latency and throughput");
target_flags &= ~MASK_INLINE_INT_DIV_THR;
}
if (ia64_fixed_range_string)
......
gcc/config/ia64/ia64.h
......@@ -85,9 +85,13 @@ extern int target_flags;
#define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
#define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
#define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
#define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */
#define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
......@@ -113,12 +117,19 @@ extern int target_flags;
#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
#define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
#define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
#define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
#define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
#define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
#define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
#define TARGET_INLINE_FLOAT_DIV \
(target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
#define TARGET_INLINE_DIV \
(target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
#define TARGET_INLINE_INT_DIV \
(target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
......@@ -165,10 +176,14 @@ extern int ia64_tls_size;
N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
N_("Generate self-relocatable code") }, \
{ "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
N_("Generate inline division, optimize for latency") }, \
{ "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
N_("Generate inline division, optimize for throughput") }, \
{ "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
N_("Generate inline floating point division, optimize for latency") },\
{ "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
N_("Generate inline floating point division, optimize for throughput") },\
{ "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
N_("Generate inline integer division, optimize for latency") }, \
{ "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
N_("Generate inline integer division, optimize for throughput") },\
{ "dwarf2-asm", MASK_DWARF2_ASM, \
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
......
gcc/config/ia64/ia64.md
......@@ -1987,7 +1987,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
......@@ -2021,7 +2021,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, op1_di, div;
......@@ -2044,7 +2044,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
......@@ -2078,7 +2078,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, op1_di, div;
......@@ -2105,7 +2105,7 @@
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
(use (match_operand:TF 3 "fr_register_operand" "f"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
......@@ -2375,7 +2375,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf;
......@@ -2391,7 +2391,7 @@
op2_tf = gen_reg_rtx (TFmode);
expand_float (op2_tf, operands[2], 0);
if (TARGET_INLINE_DIV_LAT)
if (TARGET_INLINE_INT_DIV_LAT)
emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
else
emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
......@@ -2404,7 +2404,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, div;
......@@ -2421,7 +2421,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf;
......@@ -2437,7 +2437,7 @@
op2_tf = gen_reg_rtx (TFmode);
expand_float (op2_tf, operands[2], 1);
if (TARGET_INLINE_DIV_LAT)
if (TARGET_INLINE_INT_DIV_LAT)
emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
else
emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
......@@ -2450,7 +2450,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, div;
......@@ -2471,7 +2471,7 @@
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
......@@ -2530,7 +2530,7 @@
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
......@@ -2681,10 +2681,10 @@
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_DIV_LAT)
if (TARGET_INLINE_FLOAT_DIV_LAT)
insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
......@@ -2699,7 +2699,7 @@
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
......@@ -2756,7 +2756,7 @@
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
......@@ -2990,10 +2990,10 @@
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_DIV_LAT)
if (TARGET_INLINE_FLOAT_DIV_LAT)
insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
......@@ -3009,7 +3009,7 @@
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
......@@ -3089,7 +3089,7 @@
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
......@@ -3467,10 +3467,10 @@
[(set (match_operand:TF 0 "fr_register_operand" "")
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_DIV_LAT)
if (TARGET_INLINE_FLOAT_DIV_LAT)
insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
......@@ -3487,7 +3487,7 @@
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:TF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
......@@ -3565,7 +3565,7 @@
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
......
gcc/doc/invoke.texi
......@@ -622,8 +622,9 @@ in the following sections.
@gccoptlist{
-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol
-mvolatile-asm-stop -mb-step -mregister-names -mno-sdata @gol
-mconstant-gp -mauto-pic -minline-divide-min-latency @gol
-minline-divide-max-throughput -mno-dwarf2-asm @gol
-mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol
-minline-float-divide-max-throughput -minline-int-divide-min-latency @gol
-minline-int-divide-max-throughput -mno-dwarf2-asm @gol
-mfixed-range=@var{register-range}}
@emph{D30V Options}
......@@ -9389,13 +9390,25 @@ useful when compiling kernel code.
Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
This is useful when compiling firmware code.
@item -minline-divide-min-latency
@opindex minline-divide-min-latency
Generate code for inline divides using the minimum latency algorithm.
@item -minline-divide-max-throughput
@opindex minline-divide-max-throughput
Generate code for inline divides using the maximum throughput algorithm.
@item -minline-float-divide-min-latency
@opindex minline-float-divide-min-latency
Generate code for inline divides of floating point values
using the minimum latency algorithm.
@item -minline-float-divide-max-throughput
@opindex minline-float-divide-max-throughput
Generate code for inline divides of floating point values
using the maximum throughput algorithm.
@item -minline-int-divide-min-latency
@opindex minline-int-divide-min-latency
Generate code for inline divides of integer values
using the minimum latency algorithm.
@item -minline-int-divide-max-throughput
@opindex minline-int-divide-max-throughput
Generate code for inline divides of integer values
using the maximum throughput algorithm.
@item -mno-dwarf2-asm
@itemx -mdwarf2-asm
......
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