altivec-17.c: New test.

2004-08-16  Janis Johnson  <janis187@us.ibm.com>

	* gcc.dg/altivec-17.c: New test.
	* gcc.dg/altivec-18.c: New test.

From-SVN: r86067

gcc/testsuite/ChangeLog

+2004-08-16  Janis Johnson  <janis187@us.ibm.com>
+
+	* gcc.dg/altivec-17.c: New test.
+	* gcc.dg/altivec-18.c: New test.
+
 2004-08-16  Kriang Lerdsuwanakij  <lerdsuwa@users.sourceforge.net>
 
 	PR c++/6749

gcc/testsuite/gcc.dg/altivec-17.c

+/* Verify a statement in the GCC Manual that GCC allows the use of a
+   typedef name as a vector type specifier.  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+
+typedef unsigned int ui;
+typedef signed char sc;
+__vector ui vui;
+__vector sc vsc;

gcc/testsuite/gcc.dg/altivec-18.c

+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+/* { dg-final { scan-assembler "vcmpgtub" } } */
+/* { dg-final { scan-assembler "vcmpgtsh" } } */
+/* { dg-final { scan-assembler "vcmpgtsw" } } */
+
+/* Verify a statement in the GCC Manual that vector type specifiers can
+   omit "signed" or "unsigned", with the default being "signed" for int
+   and short, and "unsigned" for char.  */
+
+#include <altivec.h>
+
+extern vector char vc1, vc2;
+extern vector short vs1, vs2;
+extern vector int vi1, vi2;
+
+int signedness (void)
+{
+    return vec_all_le (vc1, vc2) 
+           && vec_all_le (vs1, vs2)
+           && vec_all_le (vi1, vi2);
+}