lib1funcs.S: Add support for e3v5 architecture variant.

	* config/v850/lib1funcs.S: Add support for e3v5 architecture
	variant.

	* config/v850/constraints.md (Q): Define as a memory constraint.
	* config/v850/predicates.md (label_ref_operand): New predicate.
	(e3v5_shift_operand): New predicate.
	(ior_operator): New predicate.
	* config/v850/t-v850: Add e3v5 multilib.
	* config/v850/v850-protos.h (v850_adjust_insn_length): Prototype.
	(v850_gen_movdi): Prototype.
	* config/v850/v850.c: Add support for e3v5 architecture.
	Rename all uses of TARGET_V850E || TARGET_V850E2_ALL to
	TARGET_V850E_UP.
	(construct_save_jarl): Add e3v5 long JARL support.
	(v850_adjust_insn_length): New function.  Adjust length of call
	insns when using e3v5 instructions.
	(v850_gen_movdi): New function: Generate instructions to move a
	DImode value.
	* config/v850/v850.h (TARGET_CPU_v850e3v5): Define.
	(CPP_SPEC): Define __v850e3v5__ as appropriate.
	(TARGET_USE_FPU): Enable for e3v5.
	(CONST_OK_FOR_W): New macro.
	(ADJUST_INSN_LENGTH): Define.
	* config/v850/v850.md (UNSPEC_LOOP): Define.
	(attr cpu): Add v850e3v5.
	Rename all uses of TARGET_V850E2 to TARGET_V850E2V3_UP.
	(movdi): New pattern.
	(movdi_internal): New pattern.
	(cbranchsf4): Conditionalize on TARGET_USE_FPU.
	(cbranchdf4): Conditionalize on TARGET_USE_FPU.
	(cstoresf4): Likewise.
	(cstoredf4): Likewise.
	(insv): New pattern.
	(rotlso3_a): New pattern.
	(rotlsi3_b): New pattern
	(rotlsi3_v850e3v5): New pattern.
	(doloop_begin): New pattern.
	(fix_loop_counter): New pattern.
	(doloop_end): New pattern.
	(branch_normal): Add e3v5 long branch support.
	(branch_invert): Likewise.
	(branch_z_normal): Likewise.
	(branch_z_invert): Likewise.
	(branch_nz_normal): Likewise.
	(branch_nz_invert): Likewise.
	(call_internal_short): Add e3v5 register-indirect JARL support.
	(call_internal_long): Likewise.
	(call_value_internal_short): Likewise.
	(call_value_internal_long): Likewise.
	* config/v850/v850.opt (mv850e3v5, mv850e2v4): New options.
	(mloop): New option.
	* config.gcc: Add support for configuring v840e3v5 target.
	* doc/invoke.texi: Document new v850 specific command line
	options.

From-SVN: r195623

gcc/ChangeLog

+2013-01-31  Hiroyuki Ono  <hiroyuki.ono.jc@renesas.com>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* config/v850/constraints.md (Q): Define as a memory constraint.
+	* config/v850/predicates.md (label_ref_operand): New predicate.
+	(e3v5_shift_operand): New predicate.
+	(ior_operator): New predicate.
+	* config/v850/t-v850: Add e3v5 multilib.
+	* config/v850/v850-protos.h (v850_adjust_insn_length): Prototype.
+	(v850_gen_movdi): Prototype.
+	* config/v850/v850.c: Add support for e3v5 architecture.
+	Rename all uses of TARGET_V850E || TARGET_V850E2_ALL to
+	TARGET_V850E_UP.
+	(construct_save_jarl): Add e3v5 long JARL support.
+	(v850_adjust_insn_length): New function.  Adjust length of call
+	insns when using e3v5 instructions.
+	(v850_gen_movdi): New function: Generate instructions to move a
+	DImode value.
+	* config/v850/v850.h (TARGET_CPU_v850e3v5): Define.
+	(CPP_SPEC): Define __v850e3v5__ as appropriate.
+	(TARGET_USE_FPU): Enable for e3v5.
+	(CONST_OK_FOR_W): New macro.
+	(ADJUST_INSN_LENGTH): Define.
+	* config/v850/v850.md (UNSPEC_LOOP): Define.
+	(attr cpu): Add v850e3v5.
+	Rename all uses of TARGET_V850E2 to TARGET_V850E2V3_UP.
+	(movdi): New pattern.
+	(movdi_internal): New pattern.
+	(cbranchsf4): Conditionalize on TARGET_USE_FPU.
+	(cbranchdf4): Conditionalize on TARGET_USE_FPU.
+	(cstoresf4): Likewise.
+	(cstoredf4): Likewise.
+	(insv): New pattern.
+	(rotlso3_a): New pattern.
+	(rotlsi3_b): New pattern
+	(rotlsi3_v850e3v5): New pattern.
+	(doloop_begin): New pattern.
+	(fix_loop_counter): New pattern.
+	(doloop_end): New pattern.
+	(branch_normal): Add e3v5 long branch support.
+	(branch_invert): Likewise.
+	(branch_z_normal): Likewise.
+	(branch_z_invert): Likewise.
+	(branch_nz_normal): Likewise.
+	(branch_nz_invert): Likewise.
+	(call_internal_short): Add e3v5 register-indirect JARL support.
+	(call_internal_long): Likewise.
+	(call_value_internal_short): Likewise.
+	(call_value_internal_long): Likewise.
+	* config/v850/v850.opt (mv850e3v5, mv850e2v4): New options.
+	(mloop): New option.
+	* config.gcc: Add support for configuring v840e3v5 target.
+	* doc/invoke.texi: Document new v850 specific command line
+	options.
+
 2013-01-31  Paul Koning  <ni1d@arrl.net>
 
 	PR debug/55059

gcc/config.gcc

@@ -2554,6 +2554,9 @@ v850-*-rtems*)
 	;;
 v850*-*-*)
 	case ${target} in
+	v850e3v5-*-*)
+		target_cpu_default="TARGET_CPU_v850e3v5"
+		;;
 	v850e2v3-*-*)
 		target_cpu_default="TARGET_CPU_v850e2v3"
 		;;
@@ -3614,7 +3617,7 @@ case "${target}" in
 	v850*-*-*)
 		supported_defaults=cpu
 		case ${with_cpu} in
-		"" | v850e | v850e1 | v850e2 | v850es | v850e2v3)
+		"" | v850e | v850e1 | v850e2 | v850es | v850e2v3 | v850e3v5)
 			# OK
 			;;
 		*)
@@ -3741,7 +3744,7 @@ case ${target} in
 		case "x$with_cpu" in
 		x)
 			;;
-		xv850e | xv850e1 | xv850e2 | xv850e2v3)
+		xv850e | xv850e1 | xv850e2 | xv850e2v3 | xv850e3v5)
 			target_cpu_default2="TARGET_CPU_$with_cpu"
 			;;
 		xv850es)

gcc/config/v850/constraints.md

@@ -76,7 +76,7 @@
        (match_test "0")))
 
 ;;; Extra constraints.
-(define_constraint "Q"
+(define_memory_constraint "Q"
   "A memory address that does not contain a symbol address."
   (and (match_code "mem")
        (match_test "ep_memory_operand (op, mode, FALSE)")))

gcc/config/v850/predicates.md

@@ -498,6 +498,26 @@
   return op == CONST0_RTX(mode);
 })
 
+(define_predicate "label_ref_operand"
+  (match_code "label_ref")
+)
+
+
+(define_predicate "e3v5_shift_operand"
+  (match_code "const_int,reg")
+  {
+    if (CONST_INT_P (op))
+      return IN_RANGE (INTVAL (op), 0, 31);
+    return true;
+  }
+)
+
+(define_predicate "ior_operator"
+  (match_code "ior")
+{
+  return (GET_CODE (op) == IOR);
+})
+
 ;; Return true if the floating point comparison operation
 ;; given produces a canonical answer.
 (define_predicate "v850_float_z_comparison_operator"

gcc/config/v850/t-v850

@@ -20,6 +20,9 @@
 MULTILIB_OPTIONS  = m8byte-align mgcc-abi msoft-float
 MULTILIB_DIRNAMES =  8byte        gcc-abi  soft-float
 
+MULTILIB_OPTIONS  += mv850e3v5
+MULTILIB_DIRNAMES +=  v850e3v5
+
 TCFLAGS = -mno-app-regs -msmall-sld -Wa,-mwarn-signed-overflow -Wa,-mwarn-unsigned-overflow
 
 v850-c.o: $(srcdir)/config/v850/v850-c.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \

gcc/config/v850/v850-protos.h

@@ -39,6 +39,8 @@ extern char * construct_restore_jr          (rtx);
 extern char * construct_dispose_instruction (rtx);
 extern char * construct_prepare_instruction (rtx);
 extern int    ep_memory_operand             (rtx, enum machine_mode, int);
+extern int    v850_adjust_insn_length       (rtx, int);
+extern const char * v850_gen_movdi          (rtx *);
 extern rtx    v850_gen_compare              (enum rtx_code, enum machine_mode,
 					     rtx, rtx);
 extern enum machine_mode  v850_gen_float_compare (enum rtx_code,

gcc/config/v850/v850.c

@@ -824,7 +824,7 @@ output_move_single (rtx * operands)
 	    return "movhi hi0(%1),%.,%0";
 
 	  /* A random constant.  */
-	  else if (TARGET_V850E || TARGET_V850E2_ALL)
+	  else if (TARGET_V850E_UP)
 	      return "mov %1,%0";
 	  else
 	    return "movhi hi(%1),%.,%0\n\tmovea lo(%1),%0,%0";
@@ -846,7 +846,7 @@ output_move_single (rtx * operands)
 	    return "movhi hi0(%F1),%.,%0";
 
 	  /* A random constant.  */
-	else if (TARGET_V850E || TARGET_V850E2_ALL)
+	else if (TARGET_V850E_UP)
 	      return "mov %F1,%0";
 
 	  else
@@ -863,7 +863,7 @@ output_move_single (rtx * operands)
 	       || GET_CODE (src) == SYMBOL_REF
 	       || GET_CODE (src) == CONST)
 	{
-	  if (TARGET_V850E || TARGET_V850E2_ALL) 
+	  if (TARGET_V850E_UP) 
 	    return "mov hilo(%1),%0";
 	  else
 	    return "movhi hi(%1),%.,%0\n\tmovea lo(%1),%0,%0";
@@ -1018,7 +1018,7 @@ ep_memory_offset (enum machine_mode mode, int unsignedp ATTRIBUTE_UNUSED)
     case QImode:
       if (TARGET_SMALL_SLD)
 	max_offset = (1 << 4);
-      else if ((TARGET_V850E || TARGET_V850E2_ALL)
+      else if ((TARGET_V850E_UP)
 		&& unsignedp)
 	max_offset = (1 << 4);
       else
@@ -1028,7 +1028,7 @@ ep_memory_offset (enum machine_mode mode, int unsignedp ATTRIBUTE_UNUSED)
     case HImode:
       if (TARGET_SMALL_SLD)
 	max_offset = (1 << 5);
-      else if ((TARGET_V850E || TARGET_V850E2_ALL)
+      else if ((TARGET_V850E_UP)
 		&& unsignedp)
 	max_offset = (1 << 5);
       else
@@ -1656,7 +1656,7 @@ expand_prologue (void)
   /* Save/setup global registers for interrupt functions right now.  */
   if (interrupt_handler)
     {
-      if (! TARGET_DISABLE_CALLT && (TARGET_V850E || TARGET_V850E2_ALL))
+      if (! TARGET_DISABLE_CALLT && (TARGET_V850E_UP))
 	emit_insn (gen_callt_save_interrupt ());
       else
 	emit_insn (gen_save_interrupt ());
@@ -1759,7 +1759,7 @@ expand_prologue (void)
       /* Special case interrupt functions that save all registers for a call.  */
       if (interrupt_handler && ((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
 	{
-	  if (! TARGET_DISABLE_CALLT && (TARGET_V850E || TARGET_V850E2_ALL))
+	  if (! TARGET_DISABLE_CALLT && (TARGET_V850E_UP))
 	    emit_insn (gen_callt_save_all_interrupt ());
 	  else
 	    emit_insn (gen_save_all_interrupt ());
@@ -1967,7 +1967,7 @@ expand_epilogue (void)
       /* And return or use reti for interrupt handlers.  */
       if (interrupt_handler)
         {
-          if (! TARGET_DISABLE_CALLT && (TARGET_V850E || TARGET_V850E2_ALL))
+          if (! TARGET_DISABLE_CALLT && (TARGET_V850E_UP))
             emit_insn (gen_callt_return_interrupt ());
           else
             emit_jump_insn (gen_return_interrupt ());
@@ -2437,8 +2437,11 @@ construct_save_jarl (rtx op)
       else
 	sprintf (name, "__save_%s_%s", reg_names [first], reg_names [last]);
       
-      sprintf (buff, "movhi hi(%s), r0, r11\n\tmovea lo(%s), r11, r11\n\tjarl .+4, r10\n\tadd 4, r10\n\tjmp r11",
-	       name, name);
+      if (TARGET_V850E3V5_UP)
+	sprintf (buff, "mov hilo(%s), r11\n\tjarl [r11], r10", name);
+      else
+	sprintf (buff, "movhi hi(%s), r0, r11\n\tmovea lo(%s), r11, r11\n\tjarl .+4, r10\n\tadd 4, r10\n\tjmp r11",
+		 name, name);
     }
   else
     {
@@ -3048,7 +3051,7 @@ v850_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
 static int
 v850_issue_rate (void)
 {
-  return (TARGET_V850E2_ALL? 2 : 1);
+  return (TARGET_V850E2_UP ? 2 : 1);
 }
 
 /* Implement TARGET_LEGITIMATE_CONSTANT_P.  */
@@ -3082,6 +3085,32 @@ v850_memory_move_cost (enum machine_mode mode,
       return (GET_MODE_SIZE (mode) / 2) * (in ? 3 : 1);
     }
 }
+
+int
+v850_adjust_insn_length (rtx insn, int length)
+{
+  if (TARGET_V850E3V5_UP)
+    {
+      if (CALL_P (insn))
+	{
+	  if (TARGET_LONG_CALLS)
+	    {
+	      /* call_internal_long, call_value_internal_long.  */
+	      if (length == 8)
+		length = 4;
+	      if (length == 16)
+		length = 10;
+	    }
+	  else
+	    {
+	      /* call_internal_short, call_value_internal_short.  */
+	      if (length == 8)
+		length = 4;
+	    }
+	}
+    }
+  return length;
+}
 
 /* V850 specific attributes.  */
 
@@ -3102,7 +3131,6 @@ static const struct attribute_spec v850_attribute_table[] =
   { NULL,                0, 0, false, false, false, NULL, false }
 };
 
-
 static void
 v850_option_override (void)
 {
@@ -3114,6 +3142,40 @@ v850_option_override (void)
     target_flags |= MASK_DISABLE_CALLT;
 }
 
+const char *
+v850_gen_movdi (rtx * operands)
+{
+  if (REG_P (operands[0]))
+    {
+      if (REG_P (operands[1]))
+	{
+	  if (REGNO (operands[0]) == (REGNO (operands[1]) - 1))
+	    return "mov %1, %0; mov %R1, %R0";
+
+	  return "mov %R1, %R0; mov %1, %0";
+	}
+
+      if (MEM_P (operands[1]))
+	{
+	  if (REGNO (operands[0]) & 1)
+	    /* Use two load word instructions to synthesise a load double.  */
+	    return "ld.w %1, %0 ; ld.w %R1, %R0" ;
+
+	  return "ld.dw %1, %0";
+	}
+
+      return "mov %1, %0; mov %R1, %R0";
+    }
+
+  gcc_assert (REG_P (operands[1]));
+
+  if (REGNO (operands[1]) & 1)
+    /* Use two store word instructions to synthesise a store double.  */
+    return "st.w %1, %0 ; st.w %R1, %R0 ";
+  
+  return "st.dw %1, %0";
+}
+
 /* Initialize the GCC target structure.  */
 
 #undef  TARGET_OPTION_OVERRIDE

gcc/config/v850/v850.h

@@ -37,7 +37,7 @@ extern GTY(()) rtx v850_compare_op1;
 #define TARGET_CPU_v850e1	3
 #define TARGET_CPU_v850e2	4
 #define TARGET_CPU_v850e2v3	5
-
+#define TARGET_CPU_v850e3v5	6
 
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT	TARGET_CPU_generic
@@ -86,7 +86,22 @@ extern GTY(()) rtx v850_compare_op1;
 #define SUBTARGET_CPP_SPEC	"%{!mv*:-D__v850e2v3__} %{mv850e2v3:-D__v850e2v3__}"
 #endif
 
-#define TARGET_V850E2_ALL      (TARGET_V850E2 || TARGET_V850E2V3) 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_v850e3v5
+#undef  MASK_DEFAULT
+#define MASK_DEFAULT            MASK_V850E3V5
+#undef  SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC	"%{!mv*:-mv850e3v5}"
+#undef  SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC	"%{!mv*:-D__v850e3v5__} %{mv850e3v5:-D__v850e3v5__}"
+#undef  TARGET_VERSION
+#define TARGET_VERSION		fprintf (stderr, " (Renesas V850E3V5)");
+#endif
+
+#define TARGET_V850E3V5_UP ((TARGET_V850E3V5))     
+#define TARGET_V850E2V3_UP ((TARGET_V850E2V3) || TARGET_V850E3V5_UP)
+#define TARGET_V850E2_UP   ((TARGET_V850E2)   || TARGET_V850E2V3_UP)
+#define TARGET_V850E_UP    ((TARGET_V850E)    || TARGET_V850E2_UP)
+#define TARGET_ALL         ((TARGET_V850)     || TARGET_V850E_UP)
 
 #define ASM_SPEC "%{m850es:-mv850e1}%{!mv850es:%{mv*:-mv%*}} \
 %{mrelax:-mrelax} \
@@ -96,14 +111,15 @@ extern GTY(()) rtx v850_compare_op1;
 #define LINK_SPEC "%{mgcc-abi:-m v850}"
 
 #define CPP_SPEC "\
+  %{mv850e3v5:-D__v850e3v5__} \
   %{mv850e2v3:-D__v850e2v3__} \
   %{mv850e2:-D__v850e2__} \
   %{mv850es:-D__v850e1__} \
   %{mv850e1:-D__v850e1__} \
   %{mv850e:-D__v850e__} \
   %{mv850:-D__v850__} \
-  %(subtarget_cpp_spec)" \
-  " %{mep:-D__EP__}"
+  %(subtarget_cpp_spec) \
+  %{mep:-D__EP__}"
 
 #define EXTRA_SPECS \
  { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
@@ -111,7 +127,7 @@ extern GTY(()) rtx v850_compare_op1;
 
 
 /* Macro to decide when FPU instructions can be used.  */
-#define TARGET_USE_FPU  (TARGET_V850E2V3 && ! TARGET_SOFT_FLOAT)
+#define TARGET_USE_FPU  (TARGET_V850E2V3_UP && ! TARGET_SOFT_FLOAT)
 
 #define TARGET_CPU_CPP_BUILTINS()		\
   do						\
@@ -136,7 +152,7 @@ extern GTY(()) rtx v850_compare_op1;
     }						\
   while(0)
 
-#define MASK_CPU (MASK_V850 | MASK_V850E | MASK_V850E1 | MASK_V850E2 | MASK_V850E2V3)
+#define MASK_CPU (MASK_V850 | MASK_V850E | MASK_V850E1 | MASK_V850E2 | MASK_V850E2V3 | MASK_V850E3V5)
 
 /* Target machine storage layout */
 
@@ -380,7 +396,8 @@ enum reg_class
   insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_N)
 #define CONST_OK_FOR_O(VALUE) \
   insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_O)
-
+#define CONST_OK_FOR_W(VALUE) \
+  insn_const_int_ok_for_constraint (VALUE, CONSTRAINT_W)
 
 /* Stack layout; function entry, exit and calling.  */
 
@@ -797,9 +814,9 @@ typedef enum
 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) 		\
   fprintf (FILE, "\t%s %s.L%d-.L%d%s\n",				\
 	   (TARGET_BIG_SWITCH ? ".long" : ".short"),			\
-	   (0 && ! TARGET_BIG_SWITCH && (TARGET_V850E || TARGET_V850E2_ALL) ? "(" : ""),             \
+	   (0 && ! TARGET_BIG_SWITCH && (TARGET_V850E_UP) ? "(" : ""),             \
 	   VALUE, REL,							\
-	   (0 && ! TARGET_BIG_SWITCH && (TARGET_V850E || TARGET_V850E2_ALL) ? ")>>1" : ""))
+	   (0 && ! TARGET_BIG_SWITCH && (TARGET_V850E_UP) ? ")>>1" : ""))
 
 #define ASM_OUTPUT_ALIGN(FILE, LOG)	\
   if ((LOG) != 0)			\
@@ -960,4 +977,7 @@ extern tree GHS_current_section_names [(int) COUNT_OF_GHS_SECTION_KINDS];
    -isystem <path-to-build-dir>.  */
 #define NO_IMPLICIT_EXTERN_C
 
+#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
+  ((LENGTH) = v850_adjust_insn_length ((INSN), (LENGTH)))
+
 #endif /* ! GCC_V850_H */

gcc/config/v850/v850.opt

@@ -112,6 +112,17 @@ mv850e2v3
 Target Report RejectNegative Mask(V850E2V3)
 Compile for the v850e2v3 processor
 
+mv850e3v5
+Target Report RejectNegative Mask(V850E3V5)
+Compile for the v850e3v5 processor
+
+mv850e2v4
+Target RejectNegative Mask(V850E3V5) MaskExists
+
+mloop
+Target Report Mask(LOOP)
+Enable v850e3v5 loop instructions
+
 mzda=
 Target RejectNegative Joined UInteger
 Set the max size of data eligible for the ZDA area

gcc/doc/invoke.texi

@@ -956,11 +956,16 @@ See RS/6000 and PowerPC Options.
 -mtda=@var{n}  -msda=@var{n}  -mzda=@var{n} @gol
 -mapp-regs  -mno-app-regs @gol
 -mdisable-callt  -mno-disable-callt @gol
--mv850e2v3 @gol
--mv850e2 @gol
--mv850e1 -mv850es @gol
--mv850e @gol
--mv850  -mbig-switch}
+-mv850e2v3 -mv850e2 -mv850e1 -mv850es @gol
+-mv850e -mv850 -mv850e3v5 @gol
+-mloop @gol
+-mrelax @gol
+-mlong-jumps @gol
+-msoft-float @gol
+-mhard-float @gol
+-mgcc-abi @gol
+-mrh850-abi @gol
+-mbig-switch}
 
 @emph{VAX Options}
 @gccoptlist{-mg  -mgnu  -munix}
@@ -6083,7 +6088,7 @@ vectorizer passes print the source location of loops which got
 successfully vectorized.
 @item missed
 Print information about missed optimizations. Individual passes
-control which informations to include in the output. For example,
+control which information to include in the output. For example,
 
 @smallexample
 gcc -O2 -ftree-vectorize -fopt-info-vec-missed
@@ -8401,7 +8406,7 @@ requires the complete toolchain to be aware of LTO. It requires a linker with
 linker plugin support for basic functionality.  Additionally,
 @command{nm}, @command{ar} and @command{ranlib}
 need to support linker plugins to allow a full-featured build environment
-(capable of building static libraries etc). gcc provides the @command{gcc-ar},
+(capable of building static libraries etc).  GCC provides the @command{gcc-ar},
 @command{gcc-nm}, @command{gcc-ranlib} wrappers to pass the right options
 to these tools. With non fat LTO makefiles need to be modified to use them.
 
@@ -19591,26 +19596,20 @@ the first 32 kilobytes of memory.
 @opindex mv850
 Specify that the target processor is the V850.
 
-@item -mbig-switch
-@opindex mbig-switch
-Generate code suitable for big switch tables.  Use this option only if
-the assembler/linker complain about out of range branches within a switch
-table.
-
-@item -mapp-regs
-@opindex mapp-regs
-This option causes r2 and r5 to be used in the code generated by
-the compiler.  This setting is the default.
+@item -mv850e3v5
+@opindex mv850e3v5
+Specify that the target processor is the V850E3V5.  The preprocessor
+constant @samp{__v850e3v5__} is defined if this option is used.
 
-@item -mno-app-regs
-@opindex mno-app-regs
-This option causes r2 and r5 to be treated as fixed registers.
+@item -mv850e2v4
+@opindex mv850e2v4
+Specify that the target processor is the V850E3V5.  This is an alias for
+the @option{-mv850e3v5} option.
 
 @item -mv850e2v3
 @opindex mv850e2v3
 Specify that the target processor is the V850E2V3.  The preprocessor
-constant @samp{__v850e2v3__} is defined if
-this option is used.
+constant @samp{__v850e2v3__} is defined if this option is used.
 
 @item -mv850e2
 @opindex mv850e2
@@ -19634,7 +19633,7 @@ Specify that the target processor is the V850E@.  The preprocessor
 constant @samp{__v850e__} is defined if this option is used.
 
 If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
-nor @option{-mv850e2} nor @option{-mv850e2v3}
+nor @option{-mv850e2} nor @option{-mv850e2v3} nor @option{-mv850e3v5}
 are defined then a default target processor is chosen and the
 relevant @samp{__v850*__} preprocessor constant is defined.
 
@@ -19642,10 +19641,131 @@ The preprocessor constants @samp{__v850} and @samp{__v851__} are always
 defined, regardless of which processor variant is the target.
 
 @item -mdisable-callt
+@itemx -mno-disable-callt
 @opindex mdisable-callt
+@opindex mno-disable-callt
 This option suppresses generation of the @code{CALLT} instruction for the
-v850e, v850e1, v850e2 and v850e2v3 flavors of the v850 architecture.  The default is
-@option{-mno-disable-callt} which allows the @code{CALLT} instruction to be used.
+v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850
+architecture.
+
+This option is enabled by default when the RH850 ABI is
+in use (see @option{-mrh850-abi}), and disabled by default when the
+GCC ABI is in use.  If @code{CALLT} instructions are being generated
+then the C preprocessor symbol @code{__V850_CALLT__} will be defined.
+
+@item -mrelax
+@itemx -mno-relax
+@opindex mrelax
+@opindex mno-relax
+Pass on (or do not pass on) the @option{-mrelax} command line option
+to the assembler.
+
+@item -mlong-jumps
+@itemx -mno-long-jumps
+@opindex mlong-jumps
+@opindex mno-long-jumps
+Disable (or re-enable) the generation of PC-relative jump instructions.
+
+@item -msoft-float
+@itemx -mhard-float
+@opindex msoft-float
+@opindex mhard-float
+Disable (or re-enable) the generation of hardware floating point
+instructions.  This option is only significant when the target
+architecture is @samp{V850E2V3} or higher.  If hardware floating point
+instructions are being generated then the C preprocessor symbol
+@code{__FPU_OK__} will be defined, otherwise the symbol
+@code{__NO_FPU__} will be defined.
+
+@item -mloop
+@opindex mloop
+Enables the use of the e3v5 LOOP instruction.  The use of this
+instruction is not enabled by default when the e3v5 architecture is
+selected because its use is still experimental.
+
+@item -mrh850-abi
+@itemx -mghs
+@opindex mrh850-abi
+@opindex mghs
+Enables support for the RH850 version of the V850 ABI.  This is the
+default.  With this version of the ABI the following rules apply:
+
+@itemize
+@item
+Integer sized structures and unions are returned via a memory pointer
+rather than a register.
+
+@item
+Large structures and unions (more than 8 bytes in size) are passed by
+value.
+
+@item
+Functions are aligned to 16-bit boundaries.
+
+@item
+The @option{-m8byte-align} command line option is supported.
+
+@item
+The @option{-mdisable-callt} command line option is enabled by
+default.  The @option{-mno-disable-callt} command line option is not
+supported.
+@end itemize
+
+When this version of the ABI is enabled the C preprocessor symbol
+@code{__V850_RH850_ABI__} is defined.
+
+@item -mgcc-abi
+@opindex mgcc-abi
+Enables support for the old GCC version of the V850 ABI.  With this
+version of the ABI the following rules apply:
+
+@itemize
+@item
+Integer sized structures and unions are returned in register @code{r10}.
+
+@item
+Large structures and unions (more than 8 bytes in size) are passed by
+reference.
+
+@item
+Functions are aligned to 32-bit boundaries, unless optimizing for
+size.
+
+@item
+The @option{-m8byte-align} command line option is not supported.
+
+@item
+The @option{-mdisable-callt} command line option is supported but not
+enabled by default.
+@end itemize
+
+When this version of the ABI is enabled the C preprocessor symbol
+@code{__V850_GCC_ABI__} is defined.
+
+@item -m8byte-align
+@itemx -mno-8byte-align
+@opindex m8byte-align
+@opindex mno-8byte-align
+Enables support for @code{doubles} and @code{long long} types to be
+aligned on 8-byte boundaries.  The default is to restrict the
+alignment of all objects to at most 4-bytes.  When
+@option{-m8byte-align} is in effect the C preprocessor symbol
+@code{__V850_8BYTE_ALIGN__} will be defined.
+
+@item -mbig-switch
+@opindex mbig-switch
+Generate code suitable for big switch tables.  Use this option only if
+the assembler/linker complain about out of range branches within a switch
+table.
+
+@item -mapp-regs
+@opindex mapp-regs
+This option causes r2 and r5 to be used in the code generated by
+the compiler.  This setting is the default.
+
+@item -mno-app-regs
+@opindex mno-app-regs
+This option causes r2 and r5 to be treated as fixed registers.
 
 @end table
 

libgcc/ChangeLog

+2013-01-31  Nick Clifton  <nickc@redhat.com>
+
+	* config/v850/lib1funcs.S: Add support for e3v5 architecture
+	variant.
+
 2013-01-29  Georg-Johann Lay  <avr@gjlay.de>
 
 	PR target/54222
@@ -9,7 +14,7 @@
 
 2013-01-26  David Holsgrove <david.holsgrove@xilinx.com>
 
-	* config.host(microblaze*-linux*): tmake_file: Remove 
+	* config.host(microblaze*-linux*): tmake_file: Remove
 	t-slibgcc-nolc-override, add t-slibgcc-libgcc.
 	* config/microblaze/t-microblaze: Set LIB2FUNCS_EXCLUDE
 	to exclude functions from being built with libgcc.c and use

libgcc/config/v850/lib1funcs.S

@@ -81,7 +81,7 @@ ___mulsi3:
         add   r7,  r10
         jmp   [r31]
 #endif /* __v850__ */
-#if defined(__v850e__) || defined(__v850ea__) || defined(__v850e2__) || defined(__v850e2v3__)
+#if defined(__v850e__) || defined(__v850ea__) || defined(__v850e2__) || defined(__v850e2v3__) || defined(__v850e3v5__)
         /* This routine is almost unneccesarry because gcc
            generates the MUL instruction for the RTX mulsi3.
            But if someone wants to link his application with
@@ -1765,7 +1765,7 @@ __restore_all_interrupt:
 #endif /* L_save_all_interrupt */
 	
 #if defined __V850_CALLT__
-#if defined(__v850e__) || defined(__v850e1__) || defined(__v850e2__) || defined(__v850e2v3__)
+#if defined(__v850e__) || defined(__v850e1__) || defined(__v850e2__) || defined(__v850e2v3__) || defined(__v850e3v5__)
 #ifdef	L_callt_save_r2_r29
 	/* Put these functions into the call table area.  */
 	.call_table_text
@@ -2146,7 +2146,7 @@ __callt_save_r31c:	.short ctoff(.L_callt_save_r31c)
 __callt_return_r31c:	.short ctoff(.L_callt_return_r31c)		
 #endif
 
-#endif /* __v850e__ */
+#endif /* __v850e__ + */
 #endif /* __V850_CALLT__ */
 
 /*  libgcc2 routines for NEC V850.  */