(__sparclite__): Define umul_ppmm, udiv_qrnnd, and count_leading_zeros for this…

(__sparclite__): Define umul_ppmm, udiv_qrnnd, and count_leading_zeros for this sparc architecture variant.

(__sparclite__): Define umul_ppmm, udiv_qrnnd, and
count_leading_zeros for this sparc architecture variant.
(__sparc_v8__): Changed from __sparc8__.

From-SVN: r1811

gcc/longlong.h

@@ -659,7 +659,7 @@
 	     "r" ((USItype)(al)),					\
 	     "rI" ((USItype)(bl))					\
 	   __CLOBBER_CC)
-#if defined (__sparcv8__)
+#if defined (__sparc_v8__)
 #define umul_ppmm(w1, w0, u, v) \
   __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
 	   : "=r" ((USItype)(w1)),					\
@@ -674,6 +674,67 @@
 	     "r" ((USItype)(n0)),					\
 	     "r" ((USItype)(d)))
 #else
+#if defined (__sparclite__)
+/* This has hardware multiply but not divide.  It also has two additional
+   instructions scan (ffs from high bit) and divscc.  */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((unsigned long int)(w1)),				\
+	     "=r" ((unsigned long int)(w0))				\
+	   : "r" ((unsigned long int)(u)),				\
+	     "r" ((unsigned long int)(v)))
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("! Inlined udiv_qrnnd
+	wr	%%g0,%2,%%y	! Not a delayed write for sparclite
+	tst	%%g0
+	divscc	%3,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%%g1
+	divscc	%%g1,%4,%0
+	rd	%%y,%1
+	bl,a 1f
+	add	%1,%4,%1
+1:	! End of inline udiv_qrnnd"					\
+	   : "=r" ((unsigned int)(q)),					\
+	     "=r" ((unsigned int)(r))					\
+	   : "r" ((unsigned int)(n1)),					\
+	     "r" ((unsigned int)(n0)),					\
+	     "rI" ((unsigned int)(d))					\
+	   : "%g1", __AND_CLOBBER_CC)
+#define UDIV_TIME 37
+#define count_leading_zeros(count, x) \
+  __asm__ ("scan %1,0,%0"						\
+	   : "=r" ((unsigned long int)(x))				\
+	   : "r" ((unsigned long int)(count)))
+#else
 /* SPARC without integer multiplication and divide instructions.
    (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
 #define umul_ppmm(w1, w0, u, v) \
@@ -756,7 +817,8 @@
 	     "1" ((USItype)(n1)),					\
 	     "0" ((USItype)(n0)) : "%g1" __AND_CLOBBER_CC)
 #define UDIV_TIME (3+7*32)	/* 7 instructions/iteration. 32 iterations. */
-#endif /* __sparc8__ */
+#endif /* __sparclite__ */
+#endif /* __sparc_v8__ */
 #endif /* __sparc__ */
 
 #if defined (__vax__)