Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
d94d6abf
Commit
d94d6abf
authored
Nov 29, 1999
by
Bernd Schmidt
Committed by
Bernd Schmidt
Nov 29, 1999
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Delete useless patterns
From-SVN: r30699
parent
311fe27c
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
3 additions
and
91 deletions
+3
-91
gcc/ChangeLog
+3
-0
gcc/config/alpha/alpha.md
+0
-91
No files found.
gcc/ChangeLog
View file @
d94d6abf
1999
-
11
-
29
Bernd
Schmidt
<
bernds
@cygnus
.
co
.
uk
>
*
alpha
.
md
:
Delete
useless
patterns
that
tried
to
work
around
register
elimination
problems
.
*
unroll
.
c
(
loop_iterations
)
:
Don
'
t
abort
if
iteration
variable
was
made
by
loop
.
...
...
gcc/config/alpha/alpha.md
View file @
d94d6abf
...
...
@@ -670,97 +670,6 @@
s%2addq %1,%3,%0
s%2subq %1,%n3,%0")
;; These variants of the above insns can occur if the third operand
;; is the frame pointer, or other eliminable register. E.g. some
;; register holding an offset from the stack pointer. This is a
;; kludge, but there doesn't seem to be a way around it. Only
;; recognize them while reloading.
(define_insn ""
[
(set (match_operand:DI 0 "some_ni_operand" "=r,&r")
(plus:DI (plus:DI (match_operand:DI 1 "some_operand" "%r,r")
(match_operand:DI 2 "some_operand" "%r,r"))
(match_operand:DI 3 "some_operand" "IOKL,r")))]
"reload_in_progress"
"#")
(define_split
[
(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" ""))
(match_operand:DI 3 "add_operand" "")))]
"reload_completed"
[
(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"")
(define_insn ""
[
(set (match_operand:SI 0 "some_ni_operand" "=r,&r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
(match_operand:SI 2 "const48_operand" "I,I"))
(match_operand:SI 3 "some_operand" "%r,r"))
(match_operand:SI 4 "some_operand" "IOKL,r")))]
"reload_in_progress"
"#")
(define_split
[
(set (match_operand:SI 0 "register_operand" "")
(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
(match_operand:SI 3 "register_operand" ""))
(match_operand:SI 4 "add_operand" "rIOKL")))]
"reload_completed"
[
(set (match_dup 0)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
"")
(define_insn ""
[
(set (match_operand:DI 0 "some_ni_operand" "=r,&r")
(sign_extend:DI
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
(match_operand:SI 2 "const48_operand" "I,I"))
(match_operand:SI 3 "some_operand" "%r,r"))
(match_operand:SI 4 "some_operand" "IO,r"))))]
"reload_in_progress"
"#")
(define_split
[
(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI
(plus:SI (plus:SI
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "const48_operand" ""))
(match_operand:SI 3 "register_operand" ""))
(match_operand:SI 4 "sext_add_operand" ""))))]
"reload_completed"
[
(set (match_dup 5)
(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
"operands
[
5
]
= gen_lowpart (SImode, operands
[
0
]
);")
(define_insn ""
[
(set (match_operand:DI 0 "some_ni_operand" "=r,&r")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ,rJ")
(match_operand:DI 2 "const48_operand" "I,I"))
(match_operand:DI 3 "some_operand" "%r,r"))
(match_operand:DI 4 "some_operand" "IOKL,r")))]
"reload_in_progress"
"#")
(define_split
[
(set (match_operand:DI 0 "register_operand" "")
(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "const48_operand" ""))
(match_operand:DI 3 "register_operand" ""))
(match_operand:DI 4 "add_operand" "")))]
"reload_completed"
[
(set (match_dup 0)
(plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
"")
(define_insn "negsi2"
[
(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment