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riscv-gcc-1
Commit d8bf17f9 by Lars Brinkhoff Committed by Richard Henderson
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i386.c, i386.md: Change all occurences of GEN_INT (trunc_int_for_mode (...)) to gen_int_mode (...). 

        * config/i386/i386.c, config/i386/i386.md: Change all occurences
        of GEN_INT (trunc_int_for_mode (...)) to gen_int_mode (...).

From-SVN: r51186
parent 2ca08953
Showing with 41 additions and 47 deletions
gcc/ChangeLog
2002-03-22 Lars Brinkhoff <lars@nocrew.org>
* config/i386/i386.c, config/i386/i386.md: Change all occurences
of GEN_INT (trunc_int_for_mode (...)) to gen_int_mode (...).
2002-03-22 Alexandre Oliva <aoliva@redhat.com>
* flow.c (calculate_global_regs_live): Clear aux fields of
......
gcc/config/i386/i386.c
......@@ -8060,8 +8060,7 @@ ix86_expand_int_movcc (operands)
*/
tmp = expand_simple_binop (mode, AND,
tmp,
GEN_INT (trunc_int_for_mode
(cf - ct, mode)),
gen_int_mode (cf - ct, mode),
tmp, 1, OPTAB_DIRECT);
if (ct)
tmp = expand_simple_binop (mode, PLUS,
......@@ -8211,8 +8210,7 @@ ix86_expand_int_movcc (operands)
out, 1, OPTAB_DIRECT);
out = expand_simple_binop (mode, AND,
out,
GEN_INT (trunc_int_for_mode
(cf - ct, mode)),
gen_int_mode (cf - ct, mode),
out, 1, OPTAB_DIRECT);
out = expand_simple_binop (mode, PLUS,
out, GEN_INT (ct),
......@@ -8559,7 +8557,7 @@ ix86_split_to_parts (operand, parts, mode)
case XFmode:
case TFmode:
REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
parts[2] = GEN_INT (trunc_int_for_mode (l[2], SImode));
parts[2] = gen_int_mode (l[2], SImode);
break;
case DFmode:
REAL_VALUE_TO_TARGET_DOUBLE (r, l);
......@@ -8567,8 +8565,8 @@ ix86_split_to_parts (operand, parts, mode)
default:
abort ();
}
parts[1] = GEN_INT (trunc_int_for_mode (l[1], SImode));
parts[0] = GEN_INT (trunc_int_for_mode (l[0], SImode));
parts[1] = gen_int_mode (l[1], SImode);
parts[0] = gen_int_mode (l[0], SImode);
}
else
abort ();
......@@ -8603,13 +8601,13 @@ ix86_split_to_parts (operand, parts, mode)
/* Do not use shift by 32 to avoid warning on 32bit systems. */
if (HOST_BITS_PER_WIDE_INT >= 64)
parts[0]
= GEN_INT (trunc_int_for_mode
= gen_int_mode
((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
+ ((((HOST_WIDE_INT) l[1]) << 31) << 1),
DImode));
DImode);
else
parts[0] = immed_double_const (l[0], l[1], DImode);
parts[1] = GEN_INT (trunc_int_for_mode (l[2], SImode));
parts[1] = gen_int_mode (l[2], SImode);
}
else
abort ();
......@@ -9632,8 +9630,7 @@ ix86_expand_strlensi_unroll_1 (out, align_rtx)
emit_insn (gen_one_cmplsi2 (scratch, scratch));
emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
emit_insn (gen_andsi3 (tmpreg, tmpreg,
GEN_INT (trunc_int_for_mode
(0x80808080, SImode))));
gen_int_mode (0x80808080, SImode)));
emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
align_4_label);
......@@ -10752,10 +10749,10 @@ x86_initialize_trampoline (tramp, fnaddr, cxt)
plus_constant (tramp, 10),
NULL_RTX, 1, OPTAB_DIRECT);
emit_move_insn (gen_rtx_MEM (QImode, tramp),
GEN_INT (trunc_int_for_mode (0xb9, QImode)));
gen_int_mode (0xb9, QImode));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
GEN_INT (trunc_int_for_mode (0xe9, QImode)));
gen_int_mode (0xe9, QImode));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
}
else
......@@ -10768,7 +10765,7 @@ x86_initialize_trampoline (tramp, fnaddr, cxt)
{
fnaddr = copy_to_mode_reg (DImode, fnaddr);
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
GEN_INT (trunc_int_for_mode (0xbb41, HImode)));
gen_int_mode (0xbb41, HImode));
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
gen_lowpart (SImode, fnaddr));
offset += 6;
......@@ -10776,22 +10773,22 @@ x86_initialize_trampoline (tramp, fnaddr, cxt)
else
{
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
GEN_INT (trunc_int_for_mode (0xbb49, HImode)));
gen_int_mode (0xbb49, HImode));
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
fnaddr);
offset += 10;
}
/* Load static chain using movabs to r10. */
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
GEN_INT (trunc_int_for_mode (0xba49, HImode)));
gen_int_mode (0xba49, HImode));
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
cxt);
offset += 10;
/* Jump to the r11 */
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
GEN_INT (trunc_int_for_mode (0xff49, HImode)));
gen_int_mode (0xff49, HImode));
emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
GEN_INT (trunc_int_for_mode (0xe3, QImode)));
gen_int_mode (0xe3, QImode));
offset += 3;
if (offset > TRAMPOLINE_SIZE)
abort ();
......
gcc/config/i386/i386.md
......@@ -8307,8 +8307,7 @@
mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
operands[3] = gen_rtx_AND (mode, operands[0],
GEN_INT (trunc_int_for_mode (mask, mode)));
operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
})
;; %%% This used to optimize known byte-wide and operations to memory,
......@@ -9507,8 +9506,7 @@
operands[0] = force_reg (SFmode, operands[0]);
emit_move_insn (reg,
gen_lowpart (SFmode,
GEN_INT (trunc_int_for_mode (0x80000000,
SImode))));
gen_int_mode (0x80000000, SImode)));
emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
if (dest != operands[0])
emit_move_insn (dest, operands[0]);
......@@ -9602,7 +9600,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
"operands[1] = gen_int_mode (0x80000000, SImode);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_split
......@@ -9619,7 +9617,7 @@
if (size >= 12)
size = 10;
operands[0] = adjust_address (operands[0], QImode, size - 1);
operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
operands[1] = gen_int_mode (0x80, QImode);
})
(define_expand "negdf2"
......@@ -9639,8 +9637,7 @@
in register. */
rtx reg = gen_reg_rtx (DFmode);
#if HOST_BITS_PER_WIDE_INT >= 64
rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
DImode));
rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
#else
rtx imm = immed_double_const (0, 0x80000000, DImode);
#endif
......@@ -9779,7 +9776,7 @@
&& !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
(clobber (reg:CC 17))])]
"operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
"operands[4] = gen_int_mode (0x80000000, SImode);
split_di (operands+0, 1, operands+2, operands+3);")
(define_expand "negxf2"
......@@ -9970,8 +9967,7 @@
operands[0] = force_reg (SFmode, operands[0]);
emit_move_insn (reg,
gen_lowpart (SFmode,
GEN_INT (trunc_int_for_mode (0x80000000,
SImode))));
gen_int_mode (0x80000000, SImode)));
emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
if (dest != operands[0])
emit_move_insn (dest, operands[0]);
......@@ -10054,7 +10050,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
"operands[1] = gen_int_mode (~0x80000000, SImode);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_split
......@@ -10071,7 +10067,7 @@
if (size >= 12)
size = 10;
operands[0] = adjust_address (operands[0], QImode, size - 1);
operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
operands[1] = gen_int_mode (~0x80, QImode);
})
(define_expand "absdf2"
......@@ -10091,8 +10087,7 @@
in register. */
rtx reg = gen_reg_rtx (DFmode);
#if HOST_BITS_PER_WIDE_INT >= 64
rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63,
DImode));
rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
#else
rtx imm = immed_double_const (0, 0x80000000, DImode);
#endif
......@@ -10209,7 +10204,7 @@
!FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
(clobber (reg:CC 17))])]
"operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
"operands[4] = gen_int_mode (~0x80000000, SImode);
split_di (operands+0, 1, operands+2, operands+3);")
(define_expand "absxf2"
......@@ -10660,8 +10655,7 @@
[(set (match_dup 0)
(mult:DI (match_dup 1)
(match_dup 2)))]
"operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
DImode));")
"operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
......@@ -10868,8 +10862,7 @@
rtx pat;
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
Pmode));
operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
if (Pmode != SImode)
pat = gen_rtx_SUBREG (SImode, pat, 0);
......@@ -10927,8 +10920,7 @@
[(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
{
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
Pmode));
operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
})
;; This pattern can't accept a variable shift count, since shifts by
......@@ -16863,9 +16855,9 @@
(set (match_dup 0)
(and:SI (match_dup 1) (match_dup 2)))])]
"operands[2]
= GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
& GET_MODE_MASK (GET_MODE (operands[0])),
SImode));
= gen_int_mode (INTVAL (operands[2])
& GET_MODE_MASK (GET_MODE (operands[0])),
SImode);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);")
......@@ -16883,9 +16875,9 @@
(compare:CCNO (and:SI (match_dup 0) (match_dup 1))
(const_int 0)))]
"operands[1]
= GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
& GET_MODE_MASK (GET_MODE (operands[0])),
SImode));
= gen_int_mode (INTVAL (operands[1])
& GET_MODE_MASK (GET_MODE (operands[0])),
SImode);
operands[0] = gen_lowpart (SImode, operands[0]);")
(define_split
......
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