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riscv-gcc-1
Commit d803a491 by Ian Bolton Committed by Ian Bolton
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AArch64 should return CC_NZ for AND operation (part 2) 

From-SVN: r196656
parent 430b9e22
Showing with 9 additions and 4 deletions
gcc/ChangeLog
2013-03-14 Ian Bolton <ian.bolton@arm.com> 2013-03-14 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.md: (*and<mode>3nr_compare0): Use CC_NZ.
(*and_<SHIFT:optab><mode>3nr_compare0): Likewise.
2013-03-14 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return correct * config/aarch64/aarch64.c (aarch64_select_cc_mode): Return correct
CC mode for AND. CC mode for AND.
......
gcc/config/aarch64/aarch64.md
...@@ -2547,8 +2547,8 @@ ...@@ -2547,8 +2547,8 @@
) )
(define_insn "*and<mode>3nr_compare0" (define_insn "*and<mode>3nr_compare0"
[(set (reg:CC CC_REGNUM) [(set (reg:CC_NZ CC_REGNUM)
(compare:CC (compare:CC_NZ
(and:GPI (match_operand:GPI 0 "register_operand" "%r,r") (and:GPI (match_operand:GPI 0 "register_operand" "%r,r")
(match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>")) (match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
(const_int 0)))] (const_int 0)))]
...@@ -2558,8 +2558,8 @@ ...@@ -2558,8 +2558,8 @@
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
(define_insn "*and_<SHIFT:optab><mode>3nr_compare0" (define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
[(set (reg:CC CC_REGNUM) [(set (reg:CC_NZ CC_REGNUM)
(compare:CC (compare:CC_NZ
(and:GPI (SHIFT:GPI (and:GPI (SHIFT:GPI
(match_operand:GPI 0 "register_operand" "r") (match_operand:GPI 0 "register_operand" "r")
(match_operand:QI 1 "aarch64_shift_imm_<mode>" "n")) (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
......
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