mips.c (cmp_operands): Renamed from branch_cmp.

	* config/mips/mips.c (cmp_operands): Renamed from branch_cmp.
	(branch_type): Delete.
	(gen_conditional_branch, gen_conditional_move)
	(mips_gen_conditional_trap): Update after name change.  Get the
	comparison mode from cmp_operands[0].
	* config/mips/mips.h (cmp_type, branch_type): Delete.
	(cmp_operands): Renamed from branch_cmp.
	* config/mips/mips.md (cmpsi, cmpdi, cmpsf, cmpdf): Update after
	name change.  Don't set branch_type.
	(seq, sne, sgt, sge, slt, sle, sgtu, sgeu, sltu, sleu): Check the
	mode class of cmp_operands[0] rather than branch_type.  Update after
	name change.

From-SVN: r84805

gcc/ChangeLog

 2004-07-16  Richard Sandiford  <rsandifo@redhat.com>
 
+	* config/mips/mips.c (cmp_operands): Renamed from branch_cmp.
+	(branch_type): Delete.
+	(gen_conditional_branch, gen_conditional_move)
+	(mips_gen_conditional_trap): Update after name change.  Get the
+	comparison mode from cmp_operands[0].
+	* config/mips/mips.h (cmp_type, branch_type): Delete.
+	(cmp_operands): Renamed from branch_cmp.
+	* config/mips/mips.md (cmpsi, cmpdi, cmpsf, cmpdf): Update after
+	name change.  Don't set branch_type.
+	(seq, sne, sgt, sge, slt, sle, sgtu, sgeu, sltu, sleu): Check the
+	mode class of cmp_operands[0] rather than branch_type.  Update after
+	name change.
+
+2004-07-16  Richard Sandiford  <rsandifo@redhat.com>
+
 	* config/mips/mips.c (mips_rtx_costs): In mips16 code, set the cost
 	of 0...255 to 0 when inside a SET.
 

gcc/config/mips/mips.c

@@ -467,12 +467,8 @@ int set_volatile;
 /* The next branch instruction is a branch likely, not branch normal.  */
 int mips_branch_likely;
 
-/* Cached operands, and operator to compare for use in set/branch/trap
-   on condition codes.  */
-rtx branch_cmp[2];
-
-/* what type of branch to use */
-enum cmp_type branch_type;
+/* The operands passed to the last cmpMM expander.  */
+rtx cmp_operands[2];
 
 /* The target cpu for code generation.  */
 enum processor_type mips_arch;
@@ -2974,20 +2970,19 @@ get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
 void
 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
 {
-  enum cmp_type type = branch_type;
-  rtx cmp0 = branch_cmp[0];
-  rtx cmp1 = branch_cmp[1];
+  rtx cmp0 = cmp_operands[0];
+  rtx cmp1 = cmp_operands[1];
   enum machine_mode mode;
   enum rtx_code cmp_code;
   rtx reg;
   int invert;
   rtx label1, label2;
 
-  switch (type)
+  switch (GET_MODE (cmp0))
     {
-    case CMP_SI:
-    case CMP_DI:
-      mode = type == CMP_SI ? SImode : DImode;
+    case SImode:
+    case DImode:
+      mode = GET_MODE (cmp0);
       invert = 0;
       reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
 
@@ -3004,8 +2999,8 @@ gen_conditional_branch (rtx *operands, enum rtx_code test_code)
 
       break;
 
-    case CMP_SF:
-    case CMP_DF:
+    case SFmode:
+    case DFmode:
       if (! ISA_HAS_8CC)
 	reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
       else
@@ -3051,9 +3046,9 @@ gen_conditional_branch (rtx *operands, enum rtx_code test_code)
 void
 gen_conditional_move (rtx *operands)
 {
-  rtx op0 = branch_cmp[0];
-  rtx op1 = branch_cmp[1];
-  enum machine_mode mode = GET_MODE (branch_cmp[0]);
+  rtx op0 = cmp_operands[0];
+  rtx op1 = cmp_operands[1];
+  enum machine_mode mode = GET_MODE (cmp_operands[0]);
   enum rtx_code cmp_code = GET_CODE (operands[1]);
   enum rtx_code move_code = NE;
   enum machine_mode op_mode = GET_MODE (operands[0]);
@@ -3079,13 +3074,13 @@ gen_conditional_move (rtx *operands)
 	  break;
 	case GT:
 	  cmp_code = LT;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
+	  op0 = force_reg (mode, cmp_operands[1]);
+	  op1 = cmp_operands[0];
 	  break;
 	case LE:
 	  cmp_code = LT;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
+	  op0 = force_reg (mode, cmp_operands[1]);
+	  op1 = cmp_operands[0];
 	  move_code = EQ;
 	  break;
 	case LTU:
@@ -3096,13 +3091,13 @@ gen_conditional_move (rtx *operands)
 	  break;
 	case GTU:
 	  cmp_code = LTU;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
+	  op0 = force_reg (mode, cmp_operands[1]);
+	  op1 = cmp_operands[0];
 	  break;
 	case LEU:
 	  cmp_code = LTU;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
+	  op0 = force_reg (mode, cmp_operands[1]);
+	  op1 = cmp_operands[0];
 	  move_code = EQ;
 	  break;
 	default:
@@ -3140,7 +3135,7 @@ mips_gen_conditional_trap (rtx *operands)
 {
   rtx op0, op1;
   enum rtx_code cmp_code = GET_CODE (operands[0]);
-  enum machine_mode mode = GET_MODE (branch_cmp[0]);
+  enum machine_mode mode = GET_MODE (cmp_operands[0]);
 
   /* MIPS conditional trap machine instructions don't have GT or LE
      flavors, so we must invert the comparison and convert to LT and
@@ -3155,13 +3150,13 @@ mips_gen_conditional_trap (rtx *operands)
     }
   if (cmp_code == GET_CODE (operands[0]))
     {
-      op0 = force_reg (mode, branch_cmp[0]);
-      op1 = branch_cmp[1];
+      op0 = force_reg (mode, cmp_operands[0]);
+      op1 = cmp_operands[1];
     }
   else
     {
-      op0 = force_reg (mode, branch_cmp[1]);
-      op1 = branch_cmp[0];
+      op0 = force_reg (mode, cmp_operands[1]);
+      op1 = cmp_operands[0];
     }
   if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
     op1 = force_reg (mode, op1);

gcc/config/mips/mips.h

@@ -30,15 +30,6 @@ extern int	target_flags;
 
 /* MIPS external variables defined in mips.c.  */
 
-/* comparison type */
-enum cmp_type {
-  CMP_SI,				/* compare four byte integers */
-  CMP_DI,				/* compare eight byte integers */
-  CMP_SF,				/* compare single precision floats */
-  CMP_DF,				/* compare double precision floats */
-  CMP_MAX				/* max comparison type */
-};
-
 /* Which processor to schedule for.  Since there is no difference between
    a R2000 and R3000 in terms of the scheduler, we collapse them into
    just an R3000.  The elements of the enumeration must match exactly
@@ -109,8 +100,7 @@ extern int set_noat;			/* # of nested .set noat's  */
 extern int set_volatile;		/* # of nested .set volatile's  */
 extern int mips_branch_likely;		/* emit 'l' after br (branch likely) */
 extern int mips_dbx_regno[];		/* Map register # to debug register # */
-extern GTY(()) rtx branch_cmp[2];	/* operands for compare */
-extern enum cmp_type branch_type;	/* what type of branch to use */
+extern GTY(()) rtx cmp_operands[2];
 extern enum processor_type mips_arch;   /* which cpu to codegen for */
 extern enum processor_type mips_tune;   /* which cpu to schedule for */
 extern int mips_isa;			/* architectural level */

gcc/config/mips/mips.md

@@ -5456,9 +5456,8 @@ dsrl\t%3,%3,1\n\
 
 ;; Flow here is rather complex:
 ;;
-;;  1)	The cmp{si,di,sf,df} routine is called.  It deposits the
-;;	arguments into the branch_cmp array, and the type into
-;;	branch_type.  No RTL is generated.
+;;  1)	The cmp{si,di,sf,df} routine is called.  It deposits the arguments
+;;	into cmp_operands[] but generates no RTL.
 ;;
 ;;  2)	The appropriate branch define_expand is called, which then
 ;;	creates the appropriate RTL for the comparison and branch.
@@ -5476,9 +5475,8 @@ dsrl\t%3,%3,1\n\
 		    (match_operand:SI 1 "arith_operand")))]
   ""
 {
-  branch_cmp[0] = operands[0];
-  branch_cmp[1] = operands[1];
-  branch_type = CMP_SI;
+  cmp_operands[0] = operands[0];
+  cmp_operands[1] = operands[1];
   DONE;
 })
 
@@ -5488,9 +5486,8 @@ dsrl\t%3,%3,1\n\
 		    (match_operand:DI 1 "arith_operand")))]
   "TARGET_64BIT"
 {
-  branch_cmp[0] = operands[0];
-  branch_cmp[1] = operands[1];
-  branch_type = CMP_DI;
+  cmp_operands[0] = operands[0];
+  cmp_operands[1] = operands[1];
   DONE;
 })
 
@@ -5500,9 +5497,8 @@ dsrl\t%3,%3,1\n\
 		    (match_operand:DF 1 "register_operand")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
 {
-  branch_cmp[0] = operands[0];
-  branch_cmp[1] = operands[1];
-  branch_type = CMP_DF;
+  cmp_operands[0] = operands[0];
+  cmp_operands[1] = operands[1];
   DONE;
 })
 
@@ -5512,9 +5508,8 @@ dsrl\t%3,%3,1\n\
 		    (match_operand:SF 1 "register_operand")))]
   "TARGET_HARD_FLOAT"
 {
-  branch_cmp[0] = operands[0];
-  branch_cmp[1] = operands[1];
-  branch_type = CMP_SF;
+  cmp_operands[0] = operands[0];
+  cmp_operands[1] = operands[1];
   DONE;
 })
 
@@ -6018,10 +6013,10 @@ dsrl\t%3,%3,1\n\
 	       (match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (EQ, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (EQ, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6070,10 +6065,10 @@ dsrl\t%3,%3,1\n\
 	       (match_dup 2)))]
   "!TARGET_MIPS16"
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (NE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (NE, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6101,10 +6096,10 @@ dsrl\t%3,%3,1\n\
 	       (match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (GT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (GT, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6150,10 +6145,10 @@ dsrl\t%3,%3,1\n\
 	       (match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (GE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (GE, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6163,10 +6158,10 @@ dsrl\t%3,%3,1\n\
 	       (match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (LT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (LT, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6222,10 +6217,10 @@ dsrl\t%3,%3,1\n\
 	       (match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (LE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (LE, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6289,10 +6284,10 @@ dsrl\t%3,%3,1\n\
 		(match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (GTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (GTU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6338,10 +6333,10 @@ dsrl\t%3,%3,1\n\
                 (match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (GEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (GEU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6351,10 +6346,10 @@ dsrl\t%3,%3,1\n\
 		(match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (LTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (LTU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })
 
@@ -6410,10 +6405,10 @@ dsrl\t%3,%3,1\n\
 		(match_dup 2)))]
   ""
 {
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
     FAIL;
 
-  gen_int_relational (LEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  gen_int_relational (LEU, operands[0], cmp_operands[0], cmp_operands[1], NULL);
   DONE;
 })