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riscv-gcc-1
Commit d7815554 by Ulrich Weigand Committed by Ulrich Weigand
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spu_internals.h (spu_sr, [...]): Define. 

ChangeLog:

	* config/spu/spu_internals.h (spu_sr, spu_sra, spu_srqw,
	spu_srqwbyte, spu_srqwbytebc): Define.
	* config/spu/spu-builtins.def (spu_sr, spu_sra, spu_srqw,
	spu_srqwbyte, spu_srqwbytebc): New overloaded builtins.
	* config/spu/spu.md ("shrqbybi_<mode>", "shrqbi_<mode>",
	"shrqby_<mode>"): New insn-and-split patterns.
	* config/spu/spu.c (expand_builtin_args): Determine and return
	number of operands using spu_builtin_description data.
	(spu_expand_builtin_1): Use it.

testsuite/ChangeLog:

	* gcc.target/spu/intrinsics-sr.c: New test.

From-SVN: r144178
parent 64cfbcc3
Showing with 144 additions and 5 deletions
gcc/ChangeLog
2009-02-13 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/spu/spu_internals.h (spu_sr, spu_sra, spu_srqw,
spu_srqwbyte, spu_srqwbytebc): Define.
* config/spu/spu-builtins.def (spu_sr, spu_sra, spu_srqw,
spu_srqwbyte, spu_srqwbytebc): New overloaded builtins.
* config/spu/spu.md ("shrqbybi_<mode>", "shrqbi_<mode>",
"shrqby_<mode>"): New insn-and-split patterns.
* config/spu/spu.c (expand_builtin_args): Determine and return
number of operands using spu_builtin_description data.
(spu_expand_builtin_1): Use it.
2009-02-13 Steve Ellcey <sje@cup.hp.com> 2009-02-13 Steve Ellcey <sje@cup.hp.com>
PR target/38056 PR target/38056
......
gcc/config/spu/spu-builtins.def
...@@ -670,6 +670,57 @@ DEF_BUILTIN (SPU_SLQWBYTEBC_6, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_6", ...@@ -670,6 +670,57 @@ DEF_BUILTIN (SPU_SLQWBYTEBC_6, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_6",
DEF_BUILTIN (SPU_SLQWBYTEBC_7, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI)) DEF_BUILTIN (SPU_SLQWBYTEBC_7, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_8, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI)) DEF_BUILTIN (SPU_SLQWBYTEBC_8, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_9, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI)) DEF_BUILTIN (SPU_SLQWBYTEBC_9, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR, CODE_FOR_nothing, "spu_sr", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SR_0, CODE_FOR_vlshrv8hi3, "spu_sr_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SR_1, CODE_FOR_vlshrv8hi3, "spu_sr_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SR_2, CODE_FOR_vlshrv4si3, "spu_sr_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SR_3, CODE_FOR_vlshrv4si3, "spu_sr_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SR_4, CODE_FOR_vlshrv8hi3, "spu_sr_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR_5, CODE_FOR_vlshrv8hi3, "spu_sr_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR_6, CODE_FOR_vlshrv4si3, "spu_sr_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR_7, CODE_FOR_vlshrv4si3, "spu_sr_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA, CODE_FOR_nothing, "spu_sra", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRA_0, CODE_FOR_vashrv8hi3, "spu_sra_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SRA_1, CODE_FOR_vashrv8hi3, "spu_sra_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SRA_2, CODE_FOR_vashrv4si3, "spu_sra_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SRA_3, CODE_FOR_vashrv4si3, "spu_sra_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SRA_4, CODE_FOR_vashrv8hi3, "spu_sra_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA_5, CODE_FOR_vashrv8hi3, "spu_sra_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA_6, CODE_FOR_vashrv4si3, "spu_sra_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA_7, CODE_FOR_vashrv4si3, "spu_sra_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW, CODE_FOR_nothing, "spu_srqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRQW_0, CODE_FOR_shrqbi_ti, "spu_srqw_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_1, CODE_FOR_shrqbi_ti, "spu_srqw_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_2, CODE_FOR_shrqbi_ti, "spu_srqw_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_3, CODE_FOR_shrqbi_ti, "spu_srqw_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_4, CODE_FOR_shrqbi_ti, "spu_srqw_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_5, CODE_FOR_shrqbi_ti, "spu_srqw_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_6, CODE_FOR_shrqbi_ti, "spu_srqw_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_7, CODE_FOR_shrqbi_ti, "spu_srqw_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_8, CODE_FOR_shrqbi_ti, "spu_srqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_9, CODE_FOR_shrqbi_ti, "spu_srqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE, CODE_FOR_nothing, "spu_srqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRQWBYTE_0, CODE_FOR_shrqby_ti, "spu_srqwbyte_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_1, CODE_FOR_shrqby_ti, "spu_srqwbyte_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_2, CODE_FOR_shrqby_ti, "spu_srqwbyte_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_3, CODE_FOR_shrqby_ti, "spu_srqwbyte_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_4, CODE_FOR_shrqby_ti, "spu_srqwbyte_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_5, CODE_FOR_shrqby_ti, "spu_srqwbyte_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_6, CODE_FOR_shrqby_ti, "spu_srqwbyte_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_7, CODE_FOR_shrqby_ti, "spu_srqwbyte_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_8, CODE_FOR_shrqby_ti, "spu_srqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_9, CODE_FOR_shrqby_ti, "spu_srqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC, CODE_FOR_nothing, "spu_srqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRQWBYTEBC_0, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_1, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_2, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_3, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_4, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_5, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_6, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_7, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_8, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_9, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SPLATS, CODE_FOR_nothing, "spu_splats", B_OVERLOAD, _A1(SPU_BTI_VOID)) DEF_BUILTIN (SPU_SPLATS, CODE_FOR_nothing, "spu_splats", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SPLATS_0, CODE_FOR_spu_splats, "spu_splats_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTQI)) DEF_BUILTIN (SPU_SPLATS_0, CODE_FOR_spu_splats, "spu_splats_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTQI))
......
gcc/config/spu/spu.c
...@@ -5878,7 +5878,7 @@ spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p) ...@@ -5878,7 +5878,7 @@ spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p)
} }
static void static int
expand_builtin_args (struct spu_builtin_description *d, tree exp, expand_builtin_args (struct spu_builtin_description *d, tree exp,
rtx target, rtx ops[]) rtx target, rtx ops[])
{ {
...@@ -5890,13 +5890,18 @@ expand_builtin_args (struct spu_builtin_description *d, tree exp, ...@@ -5890,13 +5890,18 @@ expand_builtin_args (struct spu_builtin_description *d, tree exp,
if (d->parm[0] != SPU_BTI_VOID) if (d->parm[0] != SPU_BTI_VOID)
ops[i++] = target; ops[i++] = target;
for (a = 0; i < insn_data[icode].n_operands; i++, a++) for (a = 0; d->parm[a+1] != SPU_BTI_END_OF_PARAMS; i++, a++)
{ {
tree arg = CALL_EXPR_ARG (exp, a); tree arg = CALL_EXPR_ARG (exp, a);
if (arg == 0) if (arg == 0)
abort (); abort ();
ops[i] = expand_expr (arg, NULL_RTX, VOIDmode, 0); ops[i] = expand_expr (arg, NULL_RTX, VOIDmode, 0);
} }
/* The insn pattern may have additional operands (SCRATCH).
Return the number of actual non-SCRATCH operands. */
gcc_assert (i <= insn_data[icode].n_operands);
return i;
} }
static rtx static rtx
...@@ -5908,10 +5913,11 @@ spu_expand_builtin_1 (struct spu_builtin_description *d, ...@@ -5908,10 +5913,11 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
enum insn_code icode = d->icode; enum insn_code icode = d->icode;
enum machine_mode mode, tmode; enum machine_mode mode, tmode;
int i, p; int i, p;
int n_operands;
tree return_type; tree return_type;
/* Set up ops[] with values from arglist. */ /* Set up ops[] with values from arglist. */
expand_builtin_args (d, exp, target, ops); n_operands = expand_builtin_args (d, exp, target, ops);
/* Handle the target operand which must be operand 0. */ /* Handle the target operand which must be operand 0. */
i = 0; i = 0;
...@@ -5969,7 +5975,7 @@ spu_expand_builtin_1 (struct spu_builtin_description *d, ...@@ -5969,7 +5975,7 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
return 0; return 0;
/* Handle the rest of the operands. */ /* Handle the rest of the operands. */
for (p = 1; i < insn_data[icode].n_operands; i++, p++) for (p = 1; i < n_operands; i++, p++)
{ {
if (insn_data[d->icode].operand[i].mode != VOIDmode) if (insn_data[d->icode].operand[i].mode != VOIDmode)
mode = insn_data[d->icode].operand[i].mode; mode = insn_data[d->icode].operand[i].mode;
...@@ -6009,7 +6015,7 @@ spu_expand_builtin_1 (struct spu_builtin_description *d, ...@@ -6009,7 +6015,7 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
ops[i] = spu_force_reg (mode, ops[i]); ops[i] = spu_force_reg (mode, ops[i]);
} }
switch (insn_data[icode].n_operands) switch (n_operands)
{ {
case 0: case 0:
pat = GEN_FCN (icode) (0); pat = GEN_FCN (icode) (0);
......
gcc/config/spu/spu.md
...@@ -2401,6 +2401,27 @@ ...@@ -2401,6 +2401,27 @@
emit_insn (gen_subsi3(operands[5], GEN_INT(7), operands[2])); emit_insn (gen_subsi3(operands[5], GEN_INT(7), operands[2]));
}) })
(define_insn_and_split "shrqbybi_<mode>"
[(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
(lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
(and:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I")
(const_int -8))))
(clobber (match_scratch:SI 3 "=&r,X"))]
""
"#"
"reload_completed"
[(set (match_dup:DTI 0)
(lshiftrt:DTI (match_dup:DTI 1)
(and:SI (neg:SI (and:SI (match_dup:SI 3) (const_int -8)))
(const_int -8))))]
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[3] = GEN_INT (7 - INTVAL (operands[2]));
else
emit_insn (gen_subsi3 (operands[3], GEN_INT (7), operands[2]));
}
[(set_attr "type" "shuf")])
(define_insn "rotqmbybi_<mode>" (define_insn "rotqmbybi_<mode>"
[(set (match_operand:DTI 0 "spu_reg_operand" "=r,r") [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
(lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r") (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
...@@ -2413,6 +2434,26 @@ ...@@ -2413,6 +2434,26 @@
rotqmbyi\t%0,%1,-%H2" rotqmbyi\t%0,%1,-%H2"
[(set_attr "type" "shuf")]) [(set_attr "type" "shuf")])
(define_insn_and_split "shrqbi_<mode>"
[(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
(lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
(and:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I")
(const_int 7))))
(clobber (match_scratch:SI 3 "=&r,X"))]
""
"#"
"reload_completed"
[(set (match_dup:DTI 0)
(lshiftrt:DTI (match_dup:DTI 1)
(and:SI (neg:SI (match_dup:SI 3)) (const_int 7))))]
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[3] = GEN_INT (-INTVAL (operands[2]));
else
emit_insn (gen_subsi3 (operands[3], GEN_INT (0), operands[2]));
}
[(set_attr "type" "shuf")])
(define_insn "rotqmbi_<mode>" (define_insn "rotqmbi_<mode>"
[(set (match_operand:DTI 0 "spu_reg_operand" "=r,r") [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
(lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r") (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
...@@ -2424,6 +2465,26 @@ ...@@ -2424,6 +2465,26 @@
rotqmbii\t%0,%1,-%E2" rotqmbii\t%0,%1,-%E2"
[(set_attr "type" "shuf")]) [(set_attr "type" "shuf")])
(define_insn_and_split "shrqby_<mode>"
[(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
(lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
(mult:SI (match_operand:SI 2 "spu_nonmem_operand" "r,I")
(const_int 8))))
(clobber (match_scratch:SI 3 "=&r,X"))]
""
"#"
"reload_completed"
[(set (match_dup:DTI 0)
(lshiftrt:DTI (match_dup:DTI 1)
(mult:SI (neg:SI (match_dup:SI 3)) (const_int 8))))]
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[3] = GEN_INT (-INTVAL (operands[2]));
else
emit_insn (gen_subsi3 (operands[3], GEN_INT (0), operands[2]));
}
[(set_attr "type" "shuf")])
(define_insn "rotqmby_<mode>" (define_insn "rotqmby_<mode>"
[(set (match_operand:DTI 0 "spu_reg_operand" "=r,r") [(set (match_operand:DTI 0 "spu_reg_operand" "=r,r")
(lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r") (lshiftrt:DTI (match_operand:DTI 1 "spu_reg_operand" "r,r")
......
gcc/config/spu/spu_internals.h
...@@ -337,6 +337,11 @@ ...@@ -337,6 +337,11 @@
#define spu_slqw(ra,rb) __builtin_spu_slqw(ra,rb) #define spu_slqw(ra,rb) __builtin_spu_slqw(ra,rb)
#define spu_slqwbyte(ra,rb) __builtin_spu_slqwbyte(ra,rb) #define spu_slqwbyte(ra,rb) __builtin_spu_slqwbyte(ra,rb)
#define spu_slqwbytebc(ra,rb) __builtin_spu_slqwbytebc(ra,rb) #define spu_slqwbytebc(ra,rb) __builtin_spu_slqwbytebc(ra,rb)
#define spu_sr(ra,rb) __builtin_spu_sr(ra,rb)
#define spu_sra(ra,rb) __builtin_spu_sra(ra,rb)
#define spu_srqw(ra,rb) __builtin_spu_srqw(ra,rb)
#define spu_srqwbyte(ra,rb) __builtin_spu_srqwbyte(ra,rb)
#define spu_srqwbytebc(ra,rb) __builtin_spu_srqwbytebc(ra,rb)
#define spu_extract(ra,pos) __builtin_spu_extract(ra,pos) #define spu_extract(ra,pos) __builtin_spu_extract(ra,pos)
#define spu_insert(scalar,ra,pos) __builtin_spu_insert(scalar,ra,pos) #define spu_insert(scalar,ra,pos) __builtin_spu_insert(scalar,ra,pos)
#define spu_promote(scalar,pos) __builtin_spu_promote(scalar,pos) #define spu_promote(scalar,pos) __builtin_spu_promote(scalar,pos)
......
gcc/testsuite/ChangeLog
2009-02-13 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* gcc.target/spu/intrinsics-sr.c: New test.
2009-02-13 Steve Ellcey <sje@cup.hp.com> 2009-02-13 Steve Ellcey <sje@cup.hp.com>
PR target/38056 PR target/38056
......
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