Commit d7256bb8 by Kyrylo Tkachov Committed by Kyrylo Tkachov

[AArch64] Fix some reg-to-reg move scheduler types.

	* config/aarch64/aarch64-simd.md (move_lo_quad_<mode>):
	Change second alternative type to f_mcr.
	* config/aarch64/aarch64.md (*movsi_aarch64): Change 11th
	and 12th alternatives' types to f_mcr and f_mrc.
	(*movdi_aarch64): Same for 12th and 13th alternatives.
	(*movsf_aarch64): Change 9th alternatives' type to mov_reg.
	(aarch64_movtilow_tilow): Change type to fmov.

From-SVN: r211418
parent a4a1b5f3
2014-06-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (move_lo_quad_<mode>):
Change second alternative type to f_mcr.
* config/aarch64/aarch64.md (*movsi_aarch64): Change 11th
and 12th alternatives' types to f_mcr and f_mrc.
(*movdi_aarch64): Same for 12th and 13th alternatives.
(*movsf_aarch64): Change 9th alternatives' type to mov_reg.
(aarch64_movtilow_tilow): Change type to fmov.
2014-06-10 Jiong Wang <jiong.wang@arm.com> 2014-06-10 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs) * config/aarch64/aarch64.c (aarch64_save_or_restore_fprs)
......
...@@ -954,7 +954,7 @@ ...@@ -954,7 +954,7 @@
dup\\t%d0, %1.d[0] dup\\t%d0, %1.d[0]
fmov\\t%d0, %1 fmov\\t%d0, %1
dup\\t%d0, %1" dup\\t%d0, %1"
[(set_attr "type" "neon_dup<q>,fmov,neon_dup<q>") [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
(set_attr "simd" "yes,*,yes") (set_attr "simd" "yes,*,yes")
(set_attr "fp" "*,yes,*") (set_attr "fp" "*,yes,*")
(set_attr "length" "4")] (set_attr "length" "4")]
......
...@@ -689,7 +689,7 @@ ...@@ -689,7 +689,7 @@
fmov\\t%w0, %s1 fmov\\t%w0, %s1
fmov\\t%s0, %s1" fmov\\t%s0, %s1"
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
adr,adr,fmov,fmov,fmov") adr,adr,f_mcr,f_mrc,fmov")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")] (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
) )
...@@ -714,7 +714,7 @@ ...@@ -714,7 +714,7 @@
fmov\\t%d0, %d1 fmov\\t%d0, %d1
movi\\t%d0, %1" movi\\t%d0, %1"
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
adr,adr,fmov,fmov,fmov,fmov") adr,adr,f_mcr,f_mrc,fmov,fmov")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
) )
...@@ -809,7 +809,7 @@ ...@@ -809,7 +809,7 @@
str\\t%w1, %0 str\\t%w1, %0
mov\\t%w0, %w1" mov\\t%w0, %w1"
[(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
f_loads,f_stores,f_loads,f_stores,fmov")] f_loads,f_stores,f_loads,f_stores,mov_reg")]
) )
(define_insn "*movdf_aarch64" (define_insn "*movdf_aarch64"
...@@ -3679,7 +3679,7 @@ ...@@ -3679,7 +3679,7 @@
(truncate:DI (match_operand:TI 1 "register_operand" "w"))))] (truncate:DI (match_operand:TI 1 "register_operand" "w"))))]
"reload_completed || reload_in_progress" "reload_completed || reload_in_progress"
"fmov\\t%d0, %d1" "fmov\\t%d0, %d1"
[(set_attr "type" "f_mcr") [(set_attr "type" "fmov")
(set_attr "length" "4") (set_attr "length" "4")
]) ])
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment