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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
d6b0bb68
Commit
d6b0bb68
authored
Jul 03, 1996
by
Mike Stump
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Plain Diff
formatting tweaks
From-SVN: r12387
parent
ba0d6745
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
35 additions
and
35 deletions
+35
-35
gcc/collect2.c
+2
-2
gcc/longlong.h
+33
-33
No files found.
gcc/collect2.c
View file @
d6b0bb68
...
...
@@ -1352,13 +1352,13 @@ main (argc, argv)
unlink
(
ldout
);
/* If -r or they'll be run via some other method, don't build the
constructor or destructor list, just return now. */
constructor or destructor list, just return now.
*/
if
(
rflag
||
!
do_collecting
)
return
0
;
/* Examine the namelist with nm and search it for static constructors
and destructors to call.
Write the constructor and destructor tables to a .s file and reload. */
Write the constructor and destructor tables to a .s file and reload.
*/
scan_prog_file
(
output_file
,
PASS_FIRST
);
...
...
gcc/longlong.h
View file @
d6b0bb68
...
...
@@ -91,65 +91,65 @@
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %1,%4,%5
addc
%
0
,
%
2
,
%
3
" \
: "
=
r
" ((USItype)(sh)), \
"
=&
r
" ((USItype)(sl)) \
: "
%
r
" ((USItype)(ah)), \
"
rI
" ((USItype)(bh)), \
"
%
r
" ((USItype)(al)), \
"
rI
" ((USItype)(bl)))
: "
=
r
" ((USItype)
(sh)), \
"
=&
r
" ((USItype)
(sl)) \
: "
%
r
" ((USItype)
(ah)), \
"
rI
" ((USItype)
(bh)), \
"
%
r
" ((USItype)
(al)), \
"
rI
" ((USItype)
(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("
sub
%
1
,
%
4
,
%
5
subc
%
0
,
%
2
,
%
3
" \
: "
=
r
" ((USItype)(sh)), \
"
=&
r
" ((USItype)(sl)) \
: "
r
" ((USItype)(ah)), \
"
rI
" ((USItype)(bh)), \
"
r
" ((USItype)(al)), \
"
rI
" ((USItype)(bl)))
: "
=
r
" ((USItype)
(sh)), \
"
=&
r
" ((USItype)
(sl)) \
: "
r
" ((USItype)
(ah)), \
"
rI
" ((USItype)
(bh)), \
"
r
" ((USItype)
(al)), \
"
rI
" ((USItype)
(bl)))
#define umul_ppmm(xh, xl, m0, m1) \
do { \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("
multiplu
%
0
,
%
1
,
%
2
" \
: "
=
r
" ((USItype)(xl)) \
: "
=
r
" ((USItype)
(xl)) \
: "
r
" (__m0), \
"
r
" (__m1)); \
__asm__ ("
multmu
%
0
,
%
1
,
%
2
" \
: "
=
r
" ((USItype)(xh)) \
: "
=
r
" ((USItype)
(xh)) \
: "
r
" (__m0), \
"
r
" (__m1)); \
} while (0)
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("
dividu
%
0
,
%
3
,
%
4
" \
: "
=
r
" ((USItype)(q)), \
"
=
q
" ((USItype)(r)) \
: "
1
" ((USItype)(n1)), \
"
r
" ((USItype)(n0)), \
"
r
" ((USItype)(d)))
: "
=
r
" ((USItype)
(q)), \
"
=
q
" ((USItype)
(r)) \
: "
1
" ((USItype)
(n1)), \
"
r
" ((USItype)
(n0)), \
"
r
" ((USItype)
(d)))
#define count_leading_zeros(count, x) \
__asm__ ("
clz
%
0
,
%
1
" \
: "
=
r
" ((USItype)(count)) \
: "
r
" ((USItype)(x)))
: "
=
r
" ((USItype)
(count)) \
: "
r
" ((USItype)
(x)))
#endif /* __a29k__ */
#if defined (__arm__)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("
adds
%
1
,
%
4
,
%
5
adc
%
0
,
%
2
,
%
3
" \
: "
=
r
" ((USItype)(sh)), \
"
=&
r
" ((USItype)(sl)) \
: "
%
r
" ((USItype)(ah)), \
"
rI
" ((USItype)(bh)), \
"
%
r
" ((USItype)(al)), \
"
rI
" ((USItype)(bl)))
: "
=
r
" ((USItype)
(sh)), \
"
=&
r
" ((USItype)
(sl)) \
: "
%
r
" ((USItype)
(ah)), \
"
rI
" ((USItype)
(bh)), \
"
%
r
" ((USItype)
(al)), \
"
rI
" ((USItype)
(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("
subs
%
1
,
%
4
,
%
5
sbc
%
0
,
%
2
,
%
3
" \
: "
=
r
" ((USItype)(sh)), \
"
=&
r
" ((USItype)(sl)) \
: "
r
" ((USItype)(ah)), \
"
rI
" ((USItype)(bh)), \
"
r
" ((USItype)(al)), \
"
rI
" ((USItype)(bl)))
: "
=
r
" ((USItype)
(sh)), \
"
=&
r
" ((USItype)
(sl)) \
: "
r
" ((USItype)
(ah)), \
"
rI
" ((USItype)
(bh)), \
"
r
" ((USItype)
(al)), \
"
rI
" ((USItype)
(bl)))
#define umul_ppmm(xh, xl, a, b) \
{register USItype __t0, __t1, __t2; \
__asm__ ("
%
@
Inlined
umul_ppmm
...
...
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