Commit d65f7478 by Kazu Hirata Committed by Kazu Hirata

s390.c: Fix comment typos.

	* s390/s390.c: Fix comment typos.
	* s390/s390.h: Likewise.
	* s390/s390.md: Likewise.

From-SVN: r46557
parent 6c624f7f
2001-10-26 Kazu Hirata <kazu@hxi.com>
* s390/s390.c: Fix comment typos.
* s390/s390.h: Likewise.
* s390/s390.md: Likewise.
2001-10-26 Alexandre Oliva <aoliva@redhat.com> 2001-10-26 Alexandre Oliva <aoliva@redhat.com>
* tree-inline.c (WALK_SUBTREE_TAIL): New macro. * tree-inline.c (WALK_SUBTREE_TAIL): New macro.
......
...@@ -346,7 +346,7 @@ s390_branch_condition_mnemonic (code, inv) ...@@ -346,7 +346,7 @@ s390_branch_condition_mnemonic (code, inv)
LEVEL is the optimization level specified; 2 if `-O2' is LEVEL is the optimization level specified; 2 if `-O2' is
specified, 1 if `-O' is specified, and 0 if neither is specified. specified, 1 if `-O' is specified, and 0 if neither is specified.
SIZE is non-zero if `-Os' is specified and zero otherwise. */ SIZE is non-zero if `-Os' is specified and zero otherwise. */
void void
optimization_options (level, size) optimization_options (level, size)
...@@ -1114,7 +1114,7 @@ legitimize_pic_address (orig, reg) ...@@ -1114,7 +1114,7 @@ legitimize_pic_address (orig, reg)
{ {
/* Access local symbols PC-relative via LARL. /* Access local symbols PC-relative via LARL.
This is the same as in the non-PIC case, so it is This is the same as in the non-PIC case, so it is
handled automatically ... */ handled automatically ... */
} }
else else
{ {
...@@ -1710,7 +1710,7 @@ reg_used_in_mem_p (regno, x) ...@@ -1710,7 +1710,7 @@ reg_used_in_mem_p (regno, x)
return 0; return 0;
} }
/* Returns true if expression DEP_RTX sets a address register /* Returns true if expression DEP_RTX sets an address register
used by instruction INSN to address memory. */ used by instruction INSN to address memory. */
static int static int
...@@ -1747,7 +1747,7 @@ addr_generation_dependency_p (dep_rtx, insn) ...@@ -1747,7 +1747,7 @@ addr_generation_dependency_p (dep_rtx, insn)
register is modified and subsequently used as base or index register is modified and subsequently used as base or index
register of a memory reference, at least 4 cycles need to pass register of a memory reference, at least 4 cycles need to pass
between setting and using the register to avoid pipeline stalls. between setting and using the register to avoid pipeline stalls.
A exception is the LA instruction. A address generated by LA can An exception is the LA instruction. An address generated by LA can
be used by introducing only a one cycle stall on the pipeline. */ be used by introducing only a one cycle stall on the pipeline. */
static int static int
...@@ -2537,7 +2537,7 @@ s390_function_prologue (file, lsize) ...@@ -2537,7 +2537,7 @@ s390_function_prologue (file, lsize)
if (!optimize) if (!optimize)
{ {
/* Stupid register allocation is stupid ... /* Stupid register allocation is stupid ...
It does not always recognize the base register is used. */ It does not always recognize the base register is used. */
regs_ever_live[BASE_REGISTER] = 1; regs_ever_live[BASE_REGISTER] = 1;
} }
...@@ -2899,7 +2899,7 @@ s390_function_arg_size (mode, type) ...@@ -2899,7 +2899,7 @@ s390_function_arg_size (mode, type)
if (type) if (type)
return int_size_in_bytes (type); return int_size_in_bytes (type);
/* No type info available for some library calls ... */ /* No type info available for some library calls ... */
if (mode != BLKmode) if (mode != BLKmode)
return GET_MODE_SIZE (mode); return GET_MODE_SIZE (mode);
......
...@@ -529,7 +529,7 @@ extern enum reg_class regclass_map[]; /* smalled class containing REGNO */ ...@@ -529,7 +529,7 @@ extern enum reg_class regclass_map[]; /* smalled class containing REGNO */
((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)) ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
because the movsi and movsf patterns don't handle r/f moves. */ because the movsi and movsf patterns don't handle r/f moves. */
#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
(GET_MODE_BITSIZE (MODE) < 32 \ (GET_MODE_BITSIZE (MODE) < 32 \
...@@ -1559,7 +1559,7 @@ do { \ ...@@ -1559,7 +1559,7 @@ do { \
is set to reload_obstack, which does not live long enough. is set to reload_obstack, which does not live long enough.
Because of this we cannot use force_const_mem in addsi3. Because of this we cannot use force_const_mem in addsi3.
This leads to problems with gen_add2_insn with a constant greater This leads to problems with gen_add2_insn with a constant greater
than a short. Because of that we give a addition of greater than a short. Because of that we give an addition of greater
constants a cost of 3 (reload1.c 10096). */ constants a cost of 3 (reload1.c 10096). */
...@@ -1682,7 +1682,7 @@ do { \ ...@@ -1682,7 +1682,7 @@ do { \
#define BRANCH_COST 1 #define BRANCH_COST 1
/* Add any extra modes needed to represent the condition code. */ /* Add any extra modes needed to represent the condition code. */
#define EXTRA_CC_MODES \ #define EXTRA_CC_MODES \
CC (CCZmode, "CCZ") \ CC (CCZmode, "CCZ") \
CC (CCAmode, "CCA") \ CC (CCAmode, "CCA") \
...@@ -1692,7 +1692,7 @@ do { \ ...@@ -1692,7 +1692,7 @@ do { \
CC (CCTmode, "CCT") CC (CCTmode, "CCT")
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. */ return the mode to be used for the comparison. */
#define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
......
...@@ -2902,7 +2902,7 @@ ...@@ -2902,7 +2902,7 @@
; ;
; The following insn is used when it is known that operand one is the stack pointer, ; The following insn is used when it is known that operand one is the stack pointer,
; and operand two is small enough to fit in the displacement field ; and operand two is small enough to fit in the displacement field
; In this case, the result will be a address ; In this case, the result will be an address
; ;
(define_insn "addaddr" (define_insn "addaddr"
......
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