mips.c (mips_class_max_nregs, [...]): New functions.

2002-04-24  Matt Hiller  <hiller@redhat.com>

	* mips.c (mips_class_max_nregs, mips_register_move_cost): New
	functions.
	* mips.h (CLASS_MAX_NREGS, REGISTER_MOVE_COST): Redefine as calls
	of the corresponding functions.
	* mips-protos.h (mips_class_max_nregs, mips_register_move_cost):
	New prototypes.

2002-04-24  Matt Hiller  <hiller@redhat.com>

	* config/mips/mips.h (mips_sw_reg_names): Declare as extern.

	(ALL_COP_ADDITIONAL_REGISTER_NAMES): New macro.
	(FIRST_PSEUDO_REGISTER): Redefine considering coprocessor
	registers, adjust comment accordingly.
	(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS,
	reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGISTER_NAMES,
	DEBUG_REGISTER_NAMES, REG_ALLOC_ORDER): Adjust to include entries
	for coprocessor registers.
	(ADDITIONAL_REGISTER_NAMES): Include
	ALL_COP_ADDITIONAL_REGISTER_NAMES.

	(COP0_REG_FIRST, COP0_REG_LAST, COP0_REG_NUM,
	COP2_REG_FIRST, COP2_REG_LAST, COP2_REG_NUM,
	COP3_REG_FIRST, COP3_REG_LAST, COP3_REG_NUM,
	COP0_REG_P, COP2_REG_P, COP3_REG_P, ALL_COP_REG_P,
	COPNUM_AS_CHAR_FROM_REGNUM, COP_REG_CLASS_P): New macros.

	(mips_char_to_class): Adjust comment to include coprocessor
	constraint letters.

	* config/mips/mips.c (coprocessor_operand, coprocessor2_operand):
	New functions.
	(mips_reg_names, mips_regno_to_class): Include coprocessor
	information.
	(mips_sw_reg_names): Ditto, make non-static.
	(mips_move_1word): Handle moves to and from coprocessor registers.
	(mips_move_2words): Handle moves to and from coprocessor
	registers.
	(mips_class_max_nregs, mips_register_move_cost): Handle
	coprocessor register classes.
	(override_options): Initialize mips_char_to_class and
	mips_hard_regno_mode_ok properly for coprocessor registers.

	* config/mips/mips.md (movdi_internal, movdi_internal2,
	movsi_internal1, movsi_internal2): Add constraint-sets for
	coprocessor registers.
	* testsuite/gcc.c-torture/mipscop-1.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-1.x: Disable above if target
	isn't mips.
	* testsuite/gcc.c-torture/mipscop-2.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-2.x: Disable above if target
	isn't mips.
	* testsuite/gcc.c-torture/mipscop-3.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-3.x: Disable above if target
	isn't mips.
	* testsuite/gcc.c-torture/mipscop-4.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-4.x: Disable above if target
	isn't mips.

	* doc/tm.texi: Document feature.

From-SVN: r52765

gcc/ChangeLog

+2002-04-25  Matt Hiller  <hiller@redhat.com>
+
+	* mips.c (mips_class_max_nregs, mips_register_move_cost): New
+	functions.
+	* mips.h (CLASS_MAX_NREGS, REGISTER_MOVE_COST): Redefine as calls
+	of the corresponding functions.
+	* mips-protos.h (mips_class_max_nregs, mips_register_move_cost):
+	New prototypes.
+	
+2002-04-25  Matt Hiller  <hiller@redhat.com>
+
+	* config/mips/mips.h (mips_sw_reg_names): Declare as extern.
+
+	(ALL_COP_ADDITIONAL_REGISTER_NAMES): New macro.
+	(FIRST_PSEUDO_REGISTER): Redefine considering coprocessor
+	registers, adjust comment accordingly.
+	(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS,
+	reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGISTER_NAMES,
+	DEBUG_REGISTER_NAMES, REG_ALLOC_ORDER): Adjust to include entries
+	for coprocessor registers.
+	(ADDITIONAL_REGISTER_NAMES): Include
+	ALL_COP_ADDITIONAL_REGISTER_NAMES.
+	
+	(COP0_REG_FIRST, COP0_REG_LAST, COP0_REG_NUM,
+	COP2_REG_FIRST, COP2_REG_LAST, COP2_REG_NUM,
+	COP3_REG_FIRST, COP3_REG_LAST, COP3_REG_NUM,
+	COP0_REG_P, COP2_REG_P, COP3_REG_P, ALL_COP_REG_P,
+	COPNUM_AS_CHAR_FROM_REGNUM, COP_REG_CLASS_P): New macros.
+
+	(mips_char_to_class): Adjust comment to include coprocessor
+	constraint letters.
+
+	* config/mips/mips.c (coprocessor_operand, coprocessor2_operand):
+	New functions.
+	(mips_reg_names, mips_regno_to_class): Include coprocessor
+	information.
+	(mips_sw_reg_names): Ditto, make non-static.
+	(mips_move_1word): Handle moves to and from coprocessor registers.
+	(mips_move_2words): Handle moves to and from coprocessor
+	registers.
+	(mips_class_max_nregs, mips_register_move_cost): Handle
+	coprocessor register classes.
+	(override_options): Initialize mips_char_to_class and
+	mips_hard_regno_mode_ok properly for coprocessor registers.
+
+	* config/mips/mips.md (movdi_internal, movdi_internal2,
+	movsi_internal1, movsi_internal2): Add constraint-sets for
+	coprocessor registers.
+	* testsuite/gcc.c-torture/mipscop-1.c: New testcase.
+	* testsuite/gcc.c-torture/mipscop-1.x: Disable above if target
+	isn't mips.
+	* testsuite/gcc.c-torture/mipscop-2.c: New testcase.
+	* testsuite/gcc.c-torture/mipscop-2.x: Disable above if target
+	isn't mips.
+	* testsuite/gcc.c-torture/mipscop-3.c: New testcase.
+	* testsuite/gcc.c-torture/mipscop-3.x: Disable above if target
+	isn't mips.
+	* testsuite/gcc.c-torture/mipscop-4.c: New testcase.
+	* testsuite/gcc.c-torture/mipscop-4.x: Disable above if target
+	isn't mips.
+	
+	* doc/tm.texi: Document feature.
+
 2002-04-25  Neil Booth  <neil@daikokuya.demon.co.uk>
 
 	* integrate.c (function_attribute_inlinable_p): Simplify.

gcc/config/mips/mips-protos.h

@@ -117,6 +117,11 @@ extern int              mips_adjust_insn_length PARAMS ((rtx, int));
 extern enum reg_class	mips_secondary_reload_class PARAMS ((enum reg_class,
 							     enum machine_mode,
 							     rtx, int));
+extern int              mips_class_max_nregs PARAMS ((enum reg_class,
+						      enum machine_mode));
+extern int              mips_register_move_cost PARAMS ((enum machine_mode,
+							 enum reg_class,
+							 enum reg_class));
 extern void		mips_select_rtx_section PARAMS ((enum machine_mode,
 							 rtx));
 

gcc/config/mips/mips.md

@@ -5092,17 +5092,17 @@ move\\t%0,%z4\\n\\
    (set_attr "length"	"4,8")])
 
 (define_insn "movdi_internal"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x")
-	(match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
+	(match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
   "!TARGET_64BIT && !TARGET_MIPS16
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode)
        || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
        || operands[1] == CONST0_RTX (DImode))"
   "* return mips_move_2words (operands, insn); "
-  [(set_attr "type"	"move,arith,load,load,store,store,hilo,hilo,hilo")
+  [(set_attr "type"	"move,arith,load,load,store,store,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
    (set_attr "mode"	"DI")
-   (set_attr "length"   "8,16,8,16,8,16,8,8,8")])
+   (set_attr "length"   "8,16,8,16,8,16,8,8,8,8,8,8,8,8,8")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
@@ -5128,17 +5128,17 @@ move\\t%0,%z4\\n\\
   "")
 
 (define_insn "movdi_internal2"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a")
-	(match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
+	(match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
   "TARGET_64BIT && !TARGET_MIPS16
    && (register_operand (operands[0], DImode)
        || se_register_operand (operands[1], DImode)
        || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
        || operands[1] == CONST0_RTX (DImode))"
   "* return mips_move_2words (operands, insn); "
-  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
+  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
    (set_attr "mode"	"DI")
-   (set_attr "length"	"4,8,4,8,4,8,4,8,4,4,4,8")])
+   (set_attr "length"	"4,8,4,8,4,8,4,8,4,4,4,8,8,8,8,8,8,8")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
@@ -5524,28 +5524,28 @@ move\\t%0,%z4\\n\\
 ;; in FP registers (off by default, use -mdebugh to enable).
 
 (define_insn "movsi_internal1"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d")
-	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
+	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
   "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
    && (register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode)
        || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
   "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
+  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
    (set_attr "mode"	"SI")
-   (set_attr "length"	"4,8,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4")])
+   (set_attr "length"	"4,8,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4,4,4,8,4,4,8")])
 
 (define_insn "movsi_internal2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
-	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
+	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
   "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
    && (register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode)
        || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
   "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
+  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
    (set_attr "mode"	"SI")
-   (set_attr "length"	"4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
+   (set_attr "length"	"4,8,4,8,4,8,4,8,4,4,4,4,4,4,4,4,8,4,4,8")])
 
 ;; This is the mips16 movsi instruction.  We accept a small integer as
 ;; the source if the destination is a GP memory reference.  This is

gcc/doc/tm.texi

@@ -49,6 +49,7 @@ through the macros defined in the @file{.h} file.
 * Floating Point::      Handling floating point for cross-compilers.
 * Mode Switching::      Insertion of mode-switching instructions.
 * Target Attributes::   Defining target-specific uses of @code{__attribute__}.
+* MIPS Coprocessors::   MIPS coprocessor support and how to customize it.
 * Misc::                Everything else.
 @end menu
 
@@ -8039,6 +8040,50 @@ attributes, @code{false} otherwise.  By default, if a function has a
 target specific attribute attached to it, it will not be inlined.
 @end deftypefn
 
+@node MIPS Coprocessors
+@section Defining coprocessor specifics for MIPS targets.
+@cindex MIPS coprocessor-definition macros
+
+The MIPS specification allows MIPS implementations to have as many as 4
+coprocessors, each with as many as 32 private registers.  gcc supports
+accessing these registers and transferring values between the registers
+and memory using asm-ized variables.  For example:
+
+@smallexample
+  register unsigned int cp0count asm ("c0r1");
+  unsigned int d;
+
+  d = cp0count + 3;
+@end smallexample
+
+(``c0r1'' is the default name of register 1 in coprocessor 0; alternate
+names may be added as described below, or the default names may be
+overridden entirely in @code{SUBTARGET_CONDITIONAL_REGISTER_USAGE}.)
+
+Coprocessor registers are assumed to be epilogue-used; sets to them will
+be preserved even if it does not appear that the register is used again
+later in the function.
+
+Another note: according to the MIPS spec, coprocessor 1 (if present) is
+the FPU.  One accesses COP1 registers through standard mips
+floating-point support; they are not included in this mechanism.
+
+There is one macro used in defining the MIPS coprocessor interface which
+you may want to override in subtargets; it is described below.
+
+@table @code
+
+@item ALL_COP_ADDITIONAL_REGISTER_NAMES
+@findex ALL_COP_ADDITIONAL_REGISTER_NAMES
+A comma-separated list (with leading comma) of pairs describing the
+alternate names of coprocessor registers.  The format of each entry should be
+@smallexample
+@{ @var{alternatename}, @var{register_number}@}
+@end smallexample
+Default: empty.
+
+@end table
+
 @node Misc
 @section Miscellaneous Parameters
 @cindex parameters, miscellaneous

gcc/testsuite/gcc.c-torture/compile/mipscop-1.c

+register unsigned int cp0count asm ("$c0r1");
+
+int
+main (int argc, char *argv[])
+{
+  unsigned int d;
+
+  d = cp0count + 3;
+  printf ("%d\n", d);
+}

gcc/testsuite/gcc.c-torture/compile/mipscop-1.x

+global target_triplet
+
+if { ![istarget "*mips*"] } {
+	return 1
+}
+
+return 0
+

gcc/testsuite/gcc.c-torture/compile/mipscop-2.c

+register unsigned int c3r1 asm ("$c3r1");
+
+extern unsigned int b, c;
+
+void
+foo ()
+{
+  unsigned int a, d;
+
+  c3r1 = a;
+  b = c3r1;
+
+  c3r1 = c;
+  d = c3r1;
+  printf ("%d\n", d);
+}

gcc/testsuite/gcc.c-torture/compile/mipscop-2.x

+global target_triplet
+
+if { ![istarget "*mips*"] } {
+	return 1
+}
+
+return 0
+

gcc/testsuite/gcc.c-torture/compile/mipscop-3.c

+register unsigned int c3r1 asm ("$c3r1"), c3r2 asm ("$c3r2");
+
+extern unsigned int b, c;
+
+void
+foo ()
+{
+  unsigned int a, d;
+
+  c3r1 = a;
+  b = c3r1;
+
+  c3r2 = c;
+  d = c3r1;
+  printf ("%d\n", d);
+}

gcc/testsuite/gcc.c-torture/compile/mipscop-3.x

+global target_triplet
+
+if { ![istarget "*mips*"] } {
+	return 1
+}
+
+return 0
+

gcc/testsuite/gcc.c-torture/compile/mipscop-4.c

+register unsigned long c3r1 asm ("$c3r1"), c3r2 asm ("$c3r2");
+
+extern unsigned long b, c;
+
+void
+foo ()
+{
+  unsigned long a, d;
+
+  c3r1 = a;
+  b = c3r1;
+
+  c3r2 = c;
+  d = c3r1;
+  printf ("%d\n", d);
+}

gcc/testsuite/gcc.c-torture/compile/mipscop-4.x

+global target_triplet
+
+if { ![istarget "*mips*"] } {
+	return 1
+}
+
+return 0
+