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riscv-gcc-1
Commit d5e4ff48 by Michael Hayes Committed by Michael Hayes
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c4x.c: Convert to gen_rtx_FOO. 

	* config/c4x/c4x.c:  Convert to gen_rtx_FOO.
	Added ATTRIBUTE_UNUSED to unused function arguments.
	(rc_reg_operand): New predicate.
	(c4x_rptb_insert): New function.
	(c4x_rptb_nop_p): Recognize modified rptb_top pattern.
	(c4x_optimization_options): New function.
	* config/c4x/c4x.md: Convert to gen_rtx_FOO.
	 (decrement_and_branch_on_count): New pattern.
	 (rptb_top): Modified pattern to work with BCT optimization.
	* config/c4x/c4x.h (RC_REG): New register class.
	(rc_reg_operand): Define prototype.
	(IS_RC_REG): New macro.
	(IS_RC_OR_PSEUDO_REG): New macro.
	(IS_RC_OR_PSEUDO_REGNO): New macro.
	(OPTIMIZATION_OPTIONS): Define.

From-SVN: r23037
parent df3f6b6d
Showing with 109 additions and 44 deletions
gcc/ChangeLog
Tue Oct 13 21:38:35 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
* config/c4x/c4x.c: Convert to gen_rtx_FOO.
Added ATTRIBUTE_UNUSED to unused function arguments.
(rc_reg_operand): New predicate.
(c4x_rptb_insert): New function.
(c4x_rptb_nop_p): Recognize modified rptb_top pattern.
(c4x_optimization_options): New function.
* config/c4x/c4x.md: Convert to gen_rtx_FOO.
(decrement_and_branch_on_count): New pattern.
(rptb_top): Modified pattern to work with BCT optimization.
* config/c4x/c4x.h (RC_REG): New register class.
(rc_reg_operand): Define prototype.
(IS_RC_REG): New macro.
(IS_RC_OR_PSEUDO_REG): New macro.
(IS_RC_OR_PSEUDO_REGNO): New macro.
(OPTIMIZATION_OPTIONS): Define.
Mon Oct 12 19:57:34 1998 Jason Merrill <jason@yorick.cygnus.com> Mon Oct 12 19:57:34 1998 Jason Merrill <jason@yorick.cygnus.com>
* collect2.c (extract_init_priority): No priority is 65535. * collect2.c (extract_init_priority): No priority is 65535.
......
gcc/config/c4x/c4x.h
...@@ -300,6 +300,9 @@ extern char *c4x_rpts_cycles_string, *c4x_cpu_version_string; ...@@ -300,6 +300,9 @@ extern char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
extern void c4x_override_options (); extern void c4x_override_options ();
#define OVERRIDE_OPTIONS c4x_override_options () #define OVERRIDE_OPTIONS c4x_override_options ()
/* Define this to change the optimizations performed by default. */
extern void c4x_optimization_options ();
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL,SIZE)
/* Run Time Target Specification */ /* Run Time Target Specification */
...@@ -431,6 +434,7 @@ extern void c4x_override_options (); ...@@ -431,6 +434,7 @@ extern void c4x_override_options ();
/* Misc registers */ /* Misc registers */
#define IS_ST_REG(r) ((r) == ST_REGNO) #define IS_ST_REG(r) ((r) == ST_REGNO)
#define IS_RC_REG(r) ((r) == RC_REGNO)
#define IS_REPEAT_REG(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO)) #define IS_REPEAT_REG(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
/* Composite register sets */ /* Composite register sets */
...@@ -455,6 +459,7 @@ extern void c4x_override_options (); ...@@ -455,6 +459,7 @@ extern void c4x_override_options ();
#define IS_DP_OR_PSEUDO_REG(r) (IS_DP_REG(r) || IS_PSEUDO_REG(r)) #define IS_DP_OR_PSEUDO_REG(r) (IS_DP_REG(r) || IS_PSEUDO_REG(r))
#define IS_SP_OR_PSEUDO_REG(r) (IS_SP_REG(r) || IS_PSEUDO_REG(r)) #define IS_SP_OR_PSEUDO_REG(r) (IS_SP_REG(r) || IS_PSEUDO_REG(r))
#define IS_ST_OR_PSEUDO_REG(r) (IS_ST_REG(r) || IS_PSEUDO_REG(r)) #define IS_ST_OR_PSEUDO_REG(r) (IS_ST_REG(r) || IS_PSEUDO_REG(r))
#define IS_RC_OR_PSEUDO_REG(r) (IS_RC_REG(r) || IS_PSEUDO_REG(r))
#define IS_PSEUDO_REGNO(op) (IS_PSEUDO_REG(REGNO(op))) #define IS_PSEUDO_REGNO(op) (IS_PSEUDO_REG(REGNO(op)))
#define IS_ADDR_REGNO(op) (IS_ADDR_REG(REGNO(op))) #define IS_ADDR_REGNO(op) (IS_ADDR_REG(REGNO(op)))
...@@ -473,6 +478,7 @@ extern void c4x_override_options (); ...@@ -473,6 +478,7 @@ extern void c4x_override_options ();
#define IS_DP_OR_PSEUDO_REGNO(op) (IS_DP_OR_PSEUDO_REG(REGNO(op))) #define IS_DP_OR_PSEUDO_REGNO(op) (IS_DP_OR_PSEUDO_REG(REGNO(op)))
#define IS_SP_OR_PSEUDO_REGNO(op) (IS_SP_OR_PSEUDO_REG(REGNO(op))) #define IS_SP_OR_PSEUDO_REGNO(op) (IS_SP_OR_PSEUDO_REG(REGNO(op)))
#define IS_ST_OR_PSEUDO_REGNO(op) (IS_ST_OR_PSEUDO_REG(REGNO(op))) #define IS_ST_OR_PSEUDO_REGNO(op) (IS_ST_OR_PSEUDO_REG(REGNO(op)))
#define IS_RC_OR_PSEUDO_REGNO(op) (IS_RC_OR_PSEUDO_REG(REGNO(op)))
/* 1 for registers that have pervasive standard uses /* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */ and are not available for the register allocator. */
...@@ -628,8 +634,9 @@ enum reg_class ...@@ -628,8 +634,9 @@ enum reg_class
EXT_REGS, /* 'f' */ EXT_REGS, /* 'f' */
ADDR_REGS, /* 'a' */ ADDR_REGS, /* 'a' */
INDEX_REGS, /* 'x' */ INDEX_REGS, /* 'x' */
SP_REG, /* 'b' */
BK_REG, /* 'k' */ BK_REG, /* 'k' */
SP_REG, /* 'b' */
RC_REG, /* 'v' */
INT_REGS, /* 'c' */ INT_REGS, /* 'c' */
GENERAL_REGS, /* 'r' */ GENERAL_REGS, /* 'r' */
DP_REG, /* 'z' */ DP_REG, /* 'z' */
...@@ -649,14 +656,15 @@ enum reg_class ...@@ -649,14 +656,15 @@ enum reg_class
"EXT_REGS", \ "EXT_REGS", \
"ADDR_REGS", \ "ADDR_REGS", \
"INDEX_REGS", \ "INDEX_REGS", \
"SP_REG", \
"BK_REG", \ "BK_REG", \
"SP_REG", \
"RC_REG", \
"INT_REGS", \ "INT_REGS", \
"GENERAL_REGS", \ "GENERAL_REGS", \
"DP_REG", \ "DP_REG", \
"ST_REG", \ "ST_REG", \
"ALL_REGS" \ "ALL_REGS" \
}; }
/* Define which registers fit in which classes. /* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET This is an initializer for a vector of HARD_REG_SET
...@@ -672,8 +680,9 @@ enum reg_class ...@@ -672,8 +680,9 @@ enum reg_class
0xf00000ff, /* 'f' R0-R11 */ \ 0xf00000ff, /* 'f' R0-R11 */ \
0x0000ff00, /* 'a' AR0-AR7 */ \ 0x0000ff00, /* 'a' AR0-AR7 */ \
0x00060000, /* 'x' IR0-IR1 */ \ 0x00060000, /* 'x' IR0-IR1 */ \
0x00100000, /* 'b' SP */ \
0x00080000, /* 'k' BK */ \ 0x00080000, /* 'k' BK */ \
0x00100000, /* 'b' SP */ \
0x08000000, /* 'v' RC */ \
0x0e1eff00, /* 'c' AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */ \ 0x0e1eff00, /* 'c' AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */ \
0xfe1effff, /* 'r' R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */\ 0xfe1effff, /* 'r' R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE, BK, SP */\
0x00010000, /* 'z' DP */ \ 0x00010000, /* 'z' DP */ \
...@@ -723,6 +732,7 @@ spill registers. */ ...@@ -723,6 +732,7 @@ spill registers. */
q - r0-r7 q - r0-r7
t - r0-r1 t - r0-r1
u - r2-r3 u - r2-r3
v - repeat count (rc)
x - index register (ir0-ir1) x - index register (ir0-ir1)
y - status register (st) y - status register (st)
z - dp reg (dp) z - dp reg (dp)
...@@ -756,6 +766,7 @@ spill registers. */ ...@@ -756,6 +766,7 @@ spill registers. */
: ((CC) == 'q') ? EXT_LOW_REGS \ : ((CC) == 'q') ? EXT_LOW_REGS \
: ((CC) == 't') ? R0R1_REGS \ : ((CC) == 't') ? R0R1_REGS \
: ((CC) == 'u') ? R2R3_REGS \ : ((CC) == 'u') ? R2R3_REGS \
: ((CC) == 'v') ? RC_REG \
: ((CC) == 'x') ? INDEX_REGS \ : ((CC) == 'x') ? INDEX_REGS \
: ((CC) == 'y') ? ST_REG \ : ((CC) == 'y') ? ST_REG \
: ((CC) == 'z') ? DP_REG \ : ((CC) == 'z') ? DP_REG \
...@@ -1604,8 +1615,8 @@ extern struct rtx_def *c4x_legitimize_address (); ...@@ -1604,8 +1615,8 @@ extern struct rtx_def *c4x_legitimize_address ();
LABEL_REF, SYMBOL_REF, CONST, and HIGH codes. */ LABEL_REF, SYMBOL_REF, CONST, and HIGH codes. */
#define LEGITIMATE_CONSTANT_P(X) \ #define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X) \ ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
|| GET_CODE (X) == CONST_INT && c4x_I_constant (X)) || (GET_CODE (X) == CONST_INT && c4x_I_constant (X)))
#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X)) #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
...@@ -1774,7 +1785,7 @@ do { \ ...@@ -1774,7 +1785,7 @@ do { \
} while (0) } while (0)
/* The TI tooling uses atexit. */ /* The TI tooling uses atexit. */
#define ON_EXIT(FUNC,ARG) atexit (FUNC) #define HAVE_ATEXIT
#undef EXTRA_SECTIONS #undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors #define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
...@@ -2475,6 +2486,7 @@ extern void c4x_rptb_process (); ...@@ -2475,6 +2486,7 @@ extern void c4x_rptb_process ();
{"dp_reg_operand", {REG}}, \ {"dp_reg_operand", {REG}}, \
{"sp_reg_operand", {REG}}, \ {"sp_reg_operand", {REG}}, \
{"st_reg_operand", {REG}}, \ {"st_reg_operand", {REG}}, \
{"rc_reg_operand", {REG}}, \
{"call_operand", {REG, SYMBOL_REF}}, \ {"call_operand", {REG, SYMBOL_REF}}, \
{"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \ {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
{"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \ {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
...@@ -2535,6 +2547,10 @@ extern int stik_const_operand (); ...@@ -2535,6 +2547,10 @@ extern int stik_const_operand ();
extern int not_const_operand (); extern int not_const_operand ();
extern int parallel_operand ();
extern int reg_or_const_operand ();
extern int reg_operand (); extern int reg_operand ();
extern int reg_imm_operand (); extern int reg_imm_operand ();
...@@ -2551,6 +2567,8 @@ extern int std_reg_operand (); ...@@ -2551,6 +2567,8 @@ extern int std_reg_operand ();
extern int src_operand (); extern int src_operand ();
extern int src_hi_operand ();
extern int lsrc_operand (); extern int lsrc_operand ();
extern int tsrc_operand (); extern int tsrc_operand ();
......
gcc/config/c4x/c4x.md
...@@ -1134,8 +1134,8 @@ ...@@ -1134,8 +1134,8 @@
if (!TARGET_C3X && which_alternative == 3) if (!TARGET_C3X && which_alternative == 3)
{ {
operands[1] = gen_rtx (CONST_INT, VOIDmode, operands[1] = gen_rtx_CONST_INT (VOIDmode,
(INTVAL (operands[1]) >> 16) & 0xffff); (INTVAL (operands[1]) >> 16) & 0xffff);
return \"ldhi\\t%1,%0\"; return \"ldhi\\t%1,%0\";
} }
...@@ -2639,10 +2639,10 @@ ...@@ -2639,10 +2639,10 @@
"* "*
if (INTVAL (operands[2]) == 8) if (INTVAL (operands[2]) == 8)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lb%3\\t%1,%0\"; return \"lb%3\\t%1,%0\";
} }
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lh%3\\t%1,%0\"; return \"lh%3\\t%1,%0\";
" "
[(set_attr "type" "binarycc,binary") [(set_attr "type" "binarycc,binary")
...@@ -2661,10 +2661,10 @@ ...@@ -2661,10 +2661,10 @@
"* "*
if (INTVAL (operands[2]) == 8) if (INTVAL (operands[2]) == 8)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lb%3\\t%1,%0\"; return \"lb%3\\t%1,%0\";
} }
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lh%3\\t%1,%0\"; return \"lh%3\\t%1,%0\";
" "
[(set_attr "type" "binarycc") [(set_attr "type" "binarycc")
...@@ -2686,10 +2686,10 @@ ...@@ -2686,10 +2686,10 @@
"* "*
if (INTVAL (operands[2]) == 8) if (INTVAL (operands[2]) == 8)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lb%3\\t%1,%0\"; return \"lb%3\\t%1,%0\";
} }
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lh%3\\t%1,%0\"; return \"lh%3\\t%1,%0\";
" "
[(set_attr "type" "binarycc") [(set_attr "type" "binarycc")
...@@ -2722,10 +2722,10 @@ ...@@ -2722,10 +2722,10 @@
"* "*
if (INTVAL (operands[2]) == 8) if (INTVAL (operands[2]) == 8)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lbu%3\\t%1,%0\"; return \"lbu%3\\t%1,%0\";
} }
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lhu%3\\t%1,%0\"; return \"lhu%3\\t%1,%0\";
" "
[(set_attr "type" "binarycc,binary") [(set_attr "type" "binarycc,binary")
...@@ -2744,10 +2744,10 @@ ...@@ -2744,10 +2744,10 @@
"* "*
if (INTVAL (operands[2]) == 8) if (INTVAL (operands[2]) == 8)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lbu%3\\t%1,%0\"; return \"lbu%3\\t%1,%0\";
} }
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lhu%3\\t%1,%0\"; return \"lhu%3\\t%1,%0\";
" "
[(set_attr "type" "binarycc") [(set_attr "type" "binarycc")
...@@ -2769,10 +2769,10 @@ ...@@ -2769,10 +2769,10 @@
"* "*
if (INTVAL (operands[2]) == 8) if (INTVAL (operands[2]) == 8)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 8); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 8);
return \"lbu%3\\t%1,%0\"; return \"lbu%3\\t%1,%0\";
} }
operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[3]) / 16); operands[3] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[3]) / 16);
return \"lhu%3\\t%1,%0\"; return \"lhu%3\\t%1,%0\";
" "
[(set_attr "type" "binarycc") [(set_attr "type" "binarycc")
...@@ -2807,12 +2807,12 @@ ...@@ -2807,12 +2807,12 @@
"* "*
if (INTVAL (operands[1]) == 8) if (INTVAL (operands[1]) == 8)
{ {
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 8); operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 8);
return \"mb%2\\t%3,%0\"; return \"mb%2\\t%3,%0\";
} }
else if (INTVAL (operands[1]) == 16) else if (INTVAL (operands[1]) == 16)
{ {
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 16); operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 16);
return \"mh%2\\t%3,%0\"; return \"mh%2\\t%3,%0\";
} }
return \"lwl1\\t%3,%0\"; return \"lwl1\\t%3,%0\";
...@@ -2834,10 +2834,10 @@ ...@@ -2834,10 +2834,10 @@
"* "*
if (INTVAL (operands[1]) == 8) if (INTVAL (operands[1]) == 8)
{ {
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 8); operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 8);
return \"mb%2\\t%3,%0\"; return \"mb%2\\t%3,%0\";
} }
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) / 16); operands[2] = gen_rtx_CONST_INT (VOIDmode, INTVAL (operands[2]) / 16);
return \"mh%2\\t%3,%0\"; return \"mh%2\\t%3,%0\";
" "
[(set_attr "type" "binarycc") [(set_attr "type" "binarycc")
...@@ -3555,8 +3555,8 @@ ...@@ -3555,8 +3555,8 @@
enum rtx_code code = GET_CODE (operands[1]); enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1); rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
if (ccreg == NULL_RTX) FAIL; if (ccreg == NULL_RTX) FAIL;
emit_insn (gen_rtx (SET, QImode, operands[0], emit_insn (gen_rtx_SET (QImode, operands[0],
gen_rtx (IF_THEN_ELSE, QImode, gen_rtx_IF_THEN_ELSE (QImode,
gen_rtx (code, VOIDmode, ccreg, const0_rtx), gen_rtx (code, VOIDmode, ccreg, const0_rtx),
operands[2], operands[3]))); operands[2], operands[3])));
DONE;}") DONE;}")
...@@ -3598,8 +3598,8 @@ ...@@ -3598,8 +3598,8 @@
enum rtx_code code = GET_CODE (operands[1]); enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1); rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
if (ccreg == NULL_RTX) FAIL; if (ccreg == NULL_RTX) FAIL;
emit_insn (gen_rtx (SET, QFmode, operands[0], emit_insn (gen_rtx_SET (QFmode, operands[0],
gen_rtx (IF_THEN_ELSE, QFmode, gen_rtx_IF_THEN_ELSE (QFmode,
gen_rtx (code, VOIDmode, ccreg, const0_rtx), gen_rtx (code, VOIDmode, ccreg, const0_rtx),
operands[2], operands[3]))); operands[2], operands[3])));
DONE;}") DONE;}")
...@@ -4294,7 +4294,7 @@ ...@@ -4294,7 +4294,7 @@
else else
return \"call\\t%C0\"; return \"call\\t%C0\";
} }
if (which_alternative == 1) else
{ {
if (final_sequence) if (final_sequence)
return \"laju\\t%R0\"; return \"laju\\t%R0\";
...@@ -4341,7 +4341,7 @@ ...@@ -4341,7 +4341,7 @@
else else
return \"call\\t%C1\"; return \"call\\t%C1\";
} }
if (which_alternative == 1) else
{ {
if (final_sequence) if (final_sequence)
return \"laju\\t%R1\"; return \"laju\\t%R1\";
...@@ -4523,6 +4523,8 @@ ...@@ -4523,6 +4523,8 @@
; operand 0 is the loop depth ; operand 0 is the loop depth
; operand 1 is the loop count ; operand 1 is the loop count
; operand 2 is the start label
; operand 3 is the end label
(define_expand "repeat_block_top" (define_expand "repeat_block_top"
[(set (reg:QI 27) (match_operand:QI 1 "src_operand" "")) [(set (reg:QI 27) (match_operand:QI 1 "src_operand" ""))
(use (match_operand:QI 0 "immediate_operand" "")) (use (match_operand:QI 0 "immediate_operand" ""))
...@@ -4560,6 +4562,36 @@ ...@@ -4560,6 +4562,36 @@
[(set_attr "type" "repeat")]) [(set_attr "type" "repeat")])
(define_insn "rptb_end"
[(set (pc)
(if_then_else (ne (match_operand:QI 0 "rc_reg_operand" "v")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))
(use (reg:QI 25))
(use (reg:QI 26))
(set (match_dup 0)
(plus:QI (match_dup 0)
(const_int -1)))]
""
"*
return c4x_rptb_nop_p(insn) ? \"nop\" : \"\";"
[(set_attr "type" "repeat")])
(define_expand "decrement_and_branch_on_count"
[(parallel [(set (pc)
(if_then_else (ne (match_operand:QI 0 "rc_reg_operand" "v")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))
(use (reg:QI 25))
(use (reg:QI 26))
(set (match_dup 0) (plus:QI (match_dup 0) (const_int -1)))])]
""
"")
(define_expand "movstrqi_small2" (define_expand "movstrqi_small2"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" "")) [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
(mem:BLK (match_operand:BLK 1 "src_operand" ""))) (mem:BLK (match_operand:BLK 1 "src_operand" "")))
...@@ -4579,8 +4611,8 @@ ...@@ -4579,8 +4611,8 @@
len = INTVAL (operands[2]); len = INTVAL (operands[2]);
tmp = operands[4]; tmp = operands[4];
src_mem = gen_rtx (MEM, QImode, src); src_mem = gen_rtx_MEM (QImode, src);
dst_mem = gen_rtx (MEM, QImode, dst); dst_mem = gen_rtx_MEM (QImode, dst);
emit_insn (gen_movqi (tmp, src_mem)); emit_insn (gen_movqi (tmp, src_mem));
emit_insn (gen_addqi3_noclobber (src, src, const1_rtx)); emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
...@@ -4719,6 +4751,7 @@ ...@@ -4719,6 +4751,7 @@
output_asm_insn (\"ldi\\t%3-1,%5\", operands); output_asm_insn (\"ldi\\t%3-1,%5\", operands);
output_asm_insn (\"$1:\tsubi3\\t*%1++,*%2++,%0\", operands); output_asm_insn (\"$1:\tsubi3\\t*%1++,*%2++,%0\", operands);
output_asm_insn (\"dbeq\\t%5,$1\", operands); output_asm_insn (\"dbeq\\t%5,$1\", operands);
return \"\";
}") }")
(define_expand "cmpstrqi" (define_expand "cmpstrqi"
...@@ -5698,8 +5731,7 @@ ...@@ -5698,8 +5731,7 @@
rtx op0hi = operand_subword (operands[0], 1, 0, HImode); rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
rtx op0lo = operand_subword (operands[0], 0, 0, HImode); rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
rtx op1lo = operand_subword (operands[1], 0, 0, HImode); rtx op1lo = operand_subword (operands[1], 0, 0, HImode);
rtx count = gen_rtx (CONST_INT, VOIDmode, rtx count = gen_rtx_CONST_INT (VOIDmode, (INTVAL (operands[2]) - 32));
(INTVAL (operands[2]) - 32));
if (INTVAL (count)) if (INTVAL (count))
emit_insn (gen_ashlqi3 (op0hi, op1lo, count)); emit_insn (gen_ashlqi3 (op0hi, op1lo, count));
...@@ -5761,8 +5793,7 @@ ...@@ -5761,8 +5793,7 @@
rtx op0hi = operand_subword (operands[0], 1, 0, HImode); rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
rtx op0lo = operand_subword (operands[0], 0, 0, HImode); rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
rtx op1hi = operand_subword (operands[1], 1, 0, HImode); rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
rtx count = gen_rtx (CONST_INT, VOIDmode, rtx count = gen_rtx_CONST_INT (VOIDmode, (INTVAL (operands[2]) - 32));
(INTVAL (operands[2]) - 32));
if (INTVAL (count)) if (INTVAL (count))
emit_insn (gen_lshrqi3 (op0lo, op1hi, count)); emit_insn (gen_lshrqi3 (op0lo, op1hi, count));
...@@ -5830,15 +5861,14 @@ ...@@ -5830,15 +5861,14 @@
rtx op0hi = operand_subword (operands[0], 1, 0, HImode); rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
rtx op0lo = operand_subword (operands[0], 0, 0, HImode); rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
rtx op1hi = operand_subword (operands[1], 1, 0, HImode); rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
rtx count = gen_rtx (CONST_INT, VOIDmode, rtx count = gen_rtx_CONST_INT (VOIDmode, (INTVAL (operands[2]) - 32));
(INTVAL (operands[2]) - 32));
if (INTVAL (count)) if (INTVAL (count))
emit_insn (gen_ashrqi3 (op0lo, op1hi, count)); emit_insn (gen_ashrqi3 (op0lo, op1hi, count));
else else
emit_insn (gen_movqi (op0lo, op1hi)); emit_insn (gen_movqi (op0lo, op1hi));
emit_insn (gen_ashrqi3 (op0hi, op1hi, gen_rtx (CONST_INT, emit_insn (gen_ashrqi3 (op0hi, op1hi,
VOIDmode, 31))); gen_rtx_CONST_INT (VOIDmode, 31)));
DONE; DONE;
} }
emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2])); emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
......
gcc/config/c4x/t-c4x
...@@ -21,9 +21,6 @@ INSTALL_LIBGCC = install-multilib ...@@ -21,9 +21,6 @@ INSTALL_LIBGCC = install-multilib
# Don't make libgcc1-test since require crt0.o # Don't make libgcc1-test since require crt0.o
LIBGCC1_TEST = LIBGCC1_TEST =
# Don't make objective C because we can't compile the libraries.
LANGUAGES = c proto c++
# C[34]x has its own float and limits.h # C[34]x has its own float and limits.h
TARGET_FLOAT_H=config/c4x/c4x-float.h TARGET_FLOAT_H=config/c4x/c4x-float.h
TARGET_LIMITS_H=config/c4x/c4x-limits.h TARGET_LIMITS_H=config/c4x/c4x-limits.h
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