Commit d4a8fcaf by Uros Bizjak Committed by Uros Bizjak

re PR target/80250 (ICE in in final_scan_insn, at final.c:3025 for…

re PR target/80250 (ICE in in final_scan_insn, at final.c:3025 for __builtin_ia32_vp4dpwssds_mask builtin)

	PR target/80250
	* config/i386/sse.md (mov<IMOD4:mode>): Remove insn pattern.
	(mov<IMOD4:mode>): New expander.
	(*mov<IMOD4:mode>_internal): New insn and split pattern.

From-SVN: r246637
parent 5738fe88
2017-04-02 Uros Bizjak <ubizjak@gmail.com>
PR target/80250
* config/i386/sse.md (mov<IMOD4:mode>): Remove insn pattern.
(mov<IMOD4:mode>): New expander.
(*mov<IMOD4:mode>_internal): New insn and split pattern.
2017-03-31 Segher Boessenkool <segher@kernel.crashing.org> 2017-03-31 Segher Boessenkool <segher@kernel.crashing.org>
PR rtl-optimization/79405 PR rtl-optimization/79405
......
...@@ -19707,24 +19707,38 @@ ...@@ -19707,24 +19707,38 @@
(define_mode_attr imod4_narrow (define_mode_attr imod4_narrow
[(V64SF "V16SF") (V64SI "V16SI")]) [(V64SF "V16SF") (V64SI "V16SI")])
(define_insn "mov<mode>" (define_expand "mov<mode>"
[(set (match_operand:IMOD4 0 "nonimmediate_operand") [(set (match_operand:IMOD4 0 "nonimmediate_operand")
(match_operand:IMOD4 1 "general_operand"))] (match_operand:IMOD4 1 "vector_move_operand"))]
"TARGET_AVX512F" "TARGET_AVX512F"
"#") {
ix86_expand_vector_move (<MODE>mode, operands);
DONE;
})
(define_split (define_insn_and_split "*mov<mode>_internal"
[(set (match_operand:IMOD4 0 "register_operand") [(set (match_operand:IMOD4 0 "nonimmediate_operand" "=v,v ,m")
(match_operand:IMOD4 1 "nonimmediate_operand"))] (match_operand:IMOD4 1 "vector_move_operand" " C,vm,v"))]
"TARGET_AVX512F && reload_completed" "TARGET_AVX512F
[(set (subreg:<imod4_narrow> (match_dup 0) 0) && (register_operand (operands[0], <MODE>mode)
(subreg:<imod4_narrow> (match_dup 1) 0)) || register_operand (operands[1], <MODE>mode))"
(set (subreg:<imod4_narrow> (match_dup 0) 64) "#"
(subreg:<imod4_narrow> (match_dup 1) 64)) "&& reload_completed"
(set (subreg:<imod4_narrow> (match_dup 0) 128) [(const_int 0)]
(subreg:<imod4_narrow> (match_dup 1) 128)) {
(set (subreg:<imod4_narrow> (match_dup 0) 192) rtx op0, op1;
(subreg:<imod4_narrow> (match_dup 1) 192))]) int i;
for (i = 0; i < 4; i++)
{
op0 = simplify_subreg
(<imod4_narrow>mode, operands[0], <MODE>mode, i * 64);
op1 = simplify_subreg
(<imod4_narrow>mode, operands[1], <MODE>mode, i * 64);
emit_move_insn (op0, op1);
}
DONE;
})
(define_insn "avx5124fmaddps_4fmaddps" (define_insn "avx5124fmaddps_4fmaddps"
[(set (match_operand:V16SF 0 "register_operand" "=v") [(set (match_operand:V16SF 0 "register_operand" "=v")
......
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