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lvzhengyang
riscv-gcc-1
Commits
d4845339
Commit
d4845339
authored
Jul 20, 2001
by
Richard Henderson
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* regclass.c (N_REG_INTS): Use only 32 bits per element.
From-SVN: r44201
parent
dbd210ef
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gcc/ChangeLog
View file @
d4845339
2001-06-20 Kelley Cook <kelley.cook@home.com>
2001-07-20 Roman Lechtchinsky <rl@cs.tu-berlin.de>
* regclass.c (N_REG_INTS): Use only 32 bits per element.
2001-07-20 Kelley Cook <kelley.cook@home.com>
* doc/install.texi (sparc-sun-solaris*): Add in 4.x assembler bug
* doc/install.texi (sparc-sun-solaris*): Add in 4.x assembler bug
information. Move rest into ...
information. Move rest into ...
...
...
gcc/regclass.c
View file @
d4845339
...
@@ -140,10 +140,11 @@ HARD_REG_SET reg_class_contents[N_REG_CLASSES];
...
@@ -140,10 +140,11 @@ HARD_REG_SET reg_class_contents[N_REG_CLASSES];
/* The same information, but as an array of unsigned ints. We copy from
/* The same information, but as an array of unsigned ints. We copy from
these unsigned ints to the table above. We do this so the tm.h files
these unsigned ints to the table above. We do this so the tm.h files
do not have to be aware of the wordsize for machines with <= 64 regs. */
do not have to be aware of the wordsize for machines with <= 64 regs.
Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
#define N_REG_INTS \
#define N_REG_INTS \
((FIRST_PSEUDO_REGISTER + (
HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT
)
((FIRST_PSEUDO_REGISTER + (
32 - 1)) / 32
)
static
unsigned
int_reg_class_contents
[
N_REG_CLASSES
][
N_REG_INTS
]
static
unsigned
int_reg_class_contents
[
N_REG_CLASSES
][
N_REG_INTS
]
=
REG_CLASS_CONTENTS
;
=
REG_CLASS_CONTENTS
;
...
...
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