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riscv-gcc-1
Commit d46f42a5 by Richard Kenner
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(iordi3): Rename ior_operand to or_operand. 

(xordi3): Use or_operand and add second alternative.
(eqv): Only accept registers.

From-SVN: r7369
parent 8395de26
Showing with 9 additions and 7 deletions
gcc/config/alpha/alpha.md
...@@ -642,7 +642,7 @@ ...@@ -642,7 +642,7 @@
(define_insn "iordi3" (define_insn "iordi3"
[(set (match_operand:DI 0 "register_operand" "=r,r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
(match_operand:DI 2 "ior_operand" "rI,N")))] (match_operand:DI 2 "or_operand" "rI,N")))]
"" ""
"@ "@
bis %r1,%2,%0 bis %r1,%2,%0
...@@ -665,17 +665,19 @@ ...@@ -665,17 +665,19 @@
[(set_attr "type" "iaddlog")]) [(set_attr "type" "iaddlog")])
(define_insn "xordi3" (define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
(match_operand:DI 2 "reg_or_8bit_operand" "rI")))] (match_operand:DI 2 "or_operand" "rI,N")))]
"" ""
"xor %r1,%2,%0" "@
xor %r1,%2,%0
eqv %r1,%N2,%0"
[(set_attr "type" "iaddlog")]) [(set_attr "type" "iaddlog")])
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
(match_operand:DI 2 "reg_or_8bit_operand" "rI"))))] (match_operand:DI 2 "register_operand" "rI"))))]
"" ""
"eqv %r1,%2,%0" "eqv %r1,%2,%0"
[(set_attr "type" "iaddlog")]) [(set_attr "type" "iaddlog")])
......
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