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riscv-gcc-1
Commit d46c971d by Richard Sandiford Committed by Richard Sandiford
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mips.h (GENERATE_MULT3_SI): Check TARGET_MAD. 

	* config/mips/mips.h (GENERATE_MULT3_SI): Check TARGET_MAD.
	* config/mips/mips.md (mul[sd]i3, mul[sd]i3_internal)
	(mul[sd]i3_r4000): Redefine using :GPR.
	(mulsi3_mult3): Don't check TARGET_MAD separately.
	(muldi3_mult3): Moved after mulsi_mult3.

From-SVN: r86406
parent 5811cb27
Showing with 50 additions and 78 deletions
gcc/ChangeLog
2004-08-23 Richard Sandiford <rsandifo@redhat.com> 2004-08-23 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (GENERATE_MULT3_SI): Check TARGET_MAD.
* config/mips/mips.md (mul[sd]i3, mul[sd]i3_internal)
(mul[sd]i3_r4000): Redefine using :GPR.
(mulsi3_mult3): Don't check TARGET_MAD separately.
(muldi3_mult3): Moved after mulsi_mult3.
2004-08-23 Richard Sandiford <rsandifo@redhat.com>
* config.gcc (mips-*-*): Remove definitions of MASK_GAS and * config.gcc (mips-*-*): Remove definitions of MASK_GAS and
OBJECT_FORMAT_ELF. Set MASK_SPLIT_ADDR by default if using GNU ld. OBJECT_FORMAT_ELF. Set MASK_SPLIT_ADDR by default if using GNU ld.
* config/mips/mips.h (MASK_GAS): Delete. Shuffle later masks down. * config/mips/mips.h (MASK_GAS): Delete. Shuffle later masks down.
......
gcc/config/mips/mips.h
...@@ -779,6 +779,7 @@ extern const struct mips_cpu_info *mips_tune_info; ...@@ -779,6 +779,7 @@ extern const struct mips_cpu_info *mips_tune_info;
|| TARGET_MIPS5500 \ || TARGET_MIPS5500 \
|| TARGET_MIPS7000 \ || TARGET_MIPS7000 \
|| TARGET_MIPS9000 \ || TARGET_MIPS9000 \
|| TARGET_MAD \
|| ISA_MIPS32 \ || ISA_MIPS32 \
|| ISA_MIPS32R2 \ || ISA_MIPS32R2 \
|| ISA_MIPS64) \ || ISA_MIPS64) \
......
gcc/config/mips/mips.md
...@@ -822,18 +822,19 @@ ...@@ -822,18 +822,19 @@
;; These processors have PRId values of 0x00004220 and 0x00004300, ;; These processors have PRId values of 0x00004220 and 0x00004300,
;; respectively. ;; respectively.
(define_expand "mulsi3" (define_expand "mul<mode>3"
[(set (match_operand:SI 0 "register_operand") [(set (match_operand:GPR 0 "register_operand")
(mult:SI (match_operand:SI 1 "register_operand") (mult:GPR (match_operand:GPR 1 "register_operand")
(match_operand:SI 2 "register_operand")))] (match_operand:GPR 2 "register_operand")))]
"" ""
{ {
if (GENERATE_MULT3_SI || TARGET_MAD) if (GENERATE_MULT3_<MODE>)
emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2])); emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
else if (!TARGET_FIX_R4000) else if (!TARGET_FIX_R4000)
emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2])); emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
operands[2]));
else else
emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2])); emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
DONE; DONE;
}) })
...@@ -843,8 +844,7 @@ ...@@ -843,8 +844,7 @@
(match_operand:SI 2 "register_operand" "d,d"))) (match_operand:SI 2 "register_operand" "d,d")))
(clobber (match_scratch:SI 3 "=h,h")) (clobber (match_scratch:SI 3 "=h,h"))
(clobber (match_scratch:SI 4 "=l,X"))] (clobber (match_scratch:SI 4 "=l,X"))]
"GENERATE_MULT3_SI "GENERATE_MULT3_SI"
|| TARGET_MAD"
{ {
if (which_alternative == 1) if (which_alternative == 1)
return "mult\t%1,%2"; return "mult\t%1,%2";
...@@ -859,8 +859,19 @@ ...@@ -859,8 +859,19 @@
return "mul\t%0,%1,%2"; return "mul\t%0,%1,%2";
return "mult\t%0,%1,%2"; return "mult\t%0,%1,%2";
} }
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "muldi3_mult3"
[(set (match_operand:DI 0 "register_operand" "=d")
(mult:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=l"))]
"TARGET_64BIT && GENERATE_MULT3_DI"
"dmult\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
;; If a register gets allocated to LO, and we spill to memory, the reload ;; If a register gets allocated to LO, and we spill to memory, the reload
;; will include a move from LO to a GPR. Merge it into the multiplication ;; will include a move from LO to a GPR. Merge it into the multiplication
...@@ -888,27 +899,27 @@ ...@@ -888,27 +899,27 @@
(clobber (match_dup 3)) (clobber (match_dup 3))
(clobber (match_dup 0))])]) (clobber (match_dup 0))])])
(define_insn "mulsi3_internal" (define_insn "mul<mode>3_internal"
[(set (match_operand:SI 0 "register_operand" "=l") [(set (match_operand:GPR 0 "register_operand" "=l")
(mult:SI (match_operand:SI 1 "register_operand" "d") (mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))) (match_operand:GPR 2 "register_operand" "d")))
(clobber (match_scratch:SI 3 "=h"))] (clobber (match_scratch:GPR 3 "=h"))]
"!TARGET_FIX_R4000" "!TARGET_FIX_R4000"
"mult\t%1,%2" "<d>mult\t%1,%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "mode" "SI")]) (set_attr "mode" "<MODE>")])
(define_insn "mulsi3_r4000" (define_insn "mul<mode>3_r4000"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:GPR 0 "register_operand" "=d")
(mult:SI (match_operand:SI 1 "register_operand" "d") (mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))) (match_operand:GPR 2 "register_operand" "d")))
(clobber (match_scratch:SI 3 "=h")) (clobber (match_scratch:GPR 3 "=h"))
(clobber (match_scratch:SI 4 "=l"))] (clobber (match_scratch:GPR 4 "=l"))]
"TARGET_FIX_R4000" "TARGET_FIX_R4000"
"mult\t%1,%2\;mflo\t%0" "<d>mult\t%1,%2\;mflo\t%0"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "mode" "SI") (set_attr "mode" "<MODE>")
(set_attr "length" "8")]) (set_attr "length" "8")])
;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
;; of "mult; mflo". They have the same latency, but the first form gives ;; of "mult; mflo". They have the same latency, but the first form gives
...@@ -1284,54 +1295,6 @@ ...@@ -1284,54 +1295,6 @@
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_expand "muldi3"
[(set (match_operand:DI 0 "register_operand")
(mult:DI (match_operand:DI 1 "register_operand")
(match_operand:DI 2 "register_operand")))]
"TARGET_64BIT"
{
if (GENERATE_MULT3_DI)
emit_insn (gen_muldi3_mult3 (operands[0], operands[1], operands[2]));
else if (!TARGET_FIX_R4000)
emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
DONE;
})
(define_insn "muldi3_mult3"
[(set (match_operand:DI 0 "register_operand" "=d")
(mult:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=l"))]
"TARGET_64BIT && GENERATE_MULT3_DI"
"dmult\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
(define_insn "muldi3_internal"
[(set (match_operand:DI 0 "register_operand" "=l")
(mult:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))]
"TARGET_64BIT && !TARGET_FIX_R4000"
"dmult\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
(define_insn "muldi3_r4000"
[(set (match_operand:DI 0 "register_operand" "=d")
(mult:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=l"))]
"TARGET_64BIT && TARGET_FIX_R4000"
"dmult\t%1,%2\;mflo\t%0"
[(set_attr "type" "imul")
(set_attr "mode" "DI")
(set_attr "length" "8")])
;; ??? We could define a mulditi3 pattern when TARGET_64BIT. ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
(define_expand "mulsidi3" (define_expand "mulsidi3"
......
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