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riscv-gcc-1
Commit d435a4be by Kyrylo Tkachov Committed by Richard Earnshaw
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arm.c: Use CONST_INT_P... 

2012-09-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c: Use CONST_INT_P, CONST_DOUBLE_P, REG_P, MEM_P,
	LABEL_P, JUMP_P, CALL_P, NOTE_P, BARRIER_P consistently.
	* config/arm/arm.h: Use REG_P, MEM_P consistently.
	* config/arm/arm.md: Use CONST_INT_P, REG_P, MEM_P, CONST_DOUBLE_P
	consistently.
	* config/arm/neon.md: Use REG_P consistently.
	* config/arm/predicates.md: Use CONST_INT_P, REG_P, MEM_P
	consistently.
	* config/arm/thumb2.md: Use CONST_INT_P, REG_P consistently.
	* config/arm/vec-common.md: Use REG_P consistently.

From-SVN: r191034
parent c2b3ec18
Showing with 41 additions and 28 deletions
gcc/ChangeLog
2012-09-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c: Use CONST_INT_P, CONST_DOUBLE_P, REG_P, MEM_P,
LABEL_P, JUMP_P, CALL_P, NOTE_P, BARRIER_P consistently.
* config/arm/arm.h: Use REG_P, MEM_P consistently.
* config/arm/arm.md: Use CONST_INT_P, REG_P, MEM_P, CONST_DOUBLE_P
consistently.
* config/arm/neon.md: Use REG_P consistently.
* config/arm/predicates.md: Use CONST_INT_P, REG_P, MEM_P
consistently.
* config/arm/thumb2.md: Use CONST_INT_P, REG_P consistently.
* config/arm/vec-common.md: Use REG_P consistently.
2012-09-06 Richard Guenther <rguenther@suse.de> 2012-09-06 Richard Guenther <rguenther@suse.de>
PR tree-optimization/54498 PR tree-optimization/54498
......
gcc/config/arm/arm.h
...@@ -1262,8 +1262,8 @@ enum reg_class ...@@ -1262,8 +1262,8 @@ enum reg_class
&& CONSTANT_P (X)) \ && CONSTANT_P (X)) \
? GENERAL_REGS : \ ? GENERAL_REGS : \
(((MODE) == HImode && ! arm_arch4 \ (((MODE) == HImode && ! arm_arch4 \
&& (GET_CODE (X) == MEM \ && (MEM_P (X) \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ || ((REG_P (X) || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \ && true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS) \ ? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
...@@ -1909,10 +1909,10 @@ enum arm_auto_incmodes ...@@ -1909,10 +1909,10 @@ enum arm_auto_incmodes
REG_OK_FOR_INDEX_P (X) REG_OK_FOR_INDEX_P (X)
#define ARM_BASE_REGISTER_RTX_P(X) \ #define ARM_BASE_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
#define ARM_INDEX_REGISTER_RTX_P(X) \ #define ARM_INDEX_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
/* Specify the machine mode that this machine uses /* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */ for the index in the tablejump instruction. */
......
gcc/config/arm/neon.md
...@@ -255,7 +255,7 @@ ...@@ -255,7 +255,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (TImode, operands[1]); operands[1] = force_reg (TImode, operands[1]);
} }
}) })
...@@ -267,7 +267,7 @@ ...@@ -267,7 +267,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]); operands[1] = force_reg (<MODE>mode, operands[1]);
} }
}) })
......
gcc/config/arm/predicates.md
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
/* We don't consider registers whose class is NO_REGS /* We don't consider registers whose class is NO_REGS
to be a register operand. */ to be a register operand. */
/* XXX might have to check for lo regs only for thumb ??? */ /* XXX might have to check for lo regs only for thumb ??? */
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER && (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
}) })
...@@ -55,7 +55,7 @@ ...@@ -55,7 +55,7 @@
if (GET_CODE (op) == SUBREG) if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op); op = SUBREG_REG (op);
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) <= LAST_ARM_REGNUM && (REGNO (op) <= LAST_ARM_REGNUM
|| REGNO (op) >= FIRST_PSEUDO_REGISTER)); || REGNO (op) >= FIRST_PSEUDO_REGISTER));
}) })
...@@ -68,7 +68,7 @@ ...@@ -68,7 +68,7 @@
/* We don't consider registers whose class is NO_REGS /* We don't consider registers whose class is NO_REGS
to be a register operand. */ to be a register operand. */
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER && (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
|| REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
...@@ -178,7 +178,7 @@ ...@@ -178,7 +178,7 @@
(and (match_code "mem,reg,subreg") (and (match_code "mem,reg,subreg")
(match_test "(!CONSTANT_P (op) (match_test "(!CONSTANT_P (op)
&& (true_regnum(op) == -1 && (true_regnum(op) == -1
|| (GET_CODE (op) == REG || (REG_P (op)
&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
(define_predicate "vfp_compare_operand" (define_predicate "vfp_compare_operand"
...@@ -195,7 +195,7 @@ ...@@ -195,7 +195,7 @@
(define_predicate "index_operand" (define_predicate "index_operand"
(ior (match_operand 0 "s_register_operand") (ior (match_operand 0 "s_register_operand")
(and (match_operand 0 "immediate_operand") (and (match_operand 0 "immediate_operand")
(match_test "(GET_CODE (op) != CONST_INT (match_test "(!CONST_INT_P (op)
|| (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
;; True for operators that can be combined with a shift in ARM state. ;; True for operators that can be combined with a shift in ARM state.
...@@ -223,10 +223,10 @@ ...@@ -223,10 +223,10 @@
(and (ior (ior (and (match_code "mult") (and (ior (ior (and (match_code "mult")
(match_test "power_of_two_operand (XEXP (op, 1), mode)")) (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "rotate") (and (match_code "rotate")
(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT (match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
(and (match_code "ashift,ashiftrt,lshiftrt,rotatert") (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
(match_test "GET_CODE (XEXP (op, 1)) != CONST_INT (match_test "!CONST_INT_P (XEXP (op, 1))
|| ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
(match_test "mode == GET_MODE (op)"))) (match_test "mode == GET_MODE (op)")))
...@@ -235,7 +235,7 @@ ...@@ -235,7 +235,7 @@
(and (ior (and (match_code "mult") (and (ior (and (match_code "mult")
(match_test "power_of_two_operand (XEXP (op, 1), mode)")) (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "ashift,ashiftrt") (and (match_code "ashift,ashiftrt")
(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT (match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)"))) && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
(match_test "mode == GET_MODE (op)"))) (match_test "mode == GET_MODE (op)")))
...@@ -332,7 +332,7 @@ ...@@ -332,7 +332,7 @@
if (GET_CODE (op) == SUBREG) if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op); op = SUBREG_REG (op);
return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0)); return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
}) })
(define_predicate "di_operand" (define_predicate "di_operand"
...@@ -349,7 +349,7 @@ ...@@ -349,7 +349,7 @@
if (GET_CODE (op) == SUBREG) if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op); op = SUBREG_REG (op);
return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0)); return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
}) })
(define_predicate "soft_df_operand" (define_predicate "soft_df_operand"
...@@ -559,7 +559,7 @@ ...@@ -559,7 +559,7 @@
rtx elt = XVECEXP (op, 0, i); rtx elt = XVECEXP (op, 0, i);
int val; int val;
if (GET_CODE (elt) != CONST_INT) if (!CONST_INT_P (elt))
return false; return false;
val = INTVAL (elt); val = INTVAL (elt);
...@@ -588,7 +588,7 @@ ...@@ -588,7 +588,7 @@
rtx elt = XVECEXP (op, 0, i); rtx elt = XVECEXP (op, 0, i);
int val; int val;
if (GET_CODE (elt) != CONST_INT) if (!CONST_INT_P (elt))
return false; return false;
val = INTVAL (elt); val = INTVAL (elt);
......
gcc/config/arm/thumb2.md
...@@ -494,13 +494,13 @@ ...@@ -494,13 +494,13 @@
if (GET_CODE (operands[5]) == LT if (GET_CODE (operands[5]) == LT
&& (operands[4] == const0_rtx)) && (operands[4] == const0_rtx))
{ {
if (which_alternative != 1 && GET_CODE (operands[1]) == REG) if (which_alternative != 1 && REG_P (operands[1]))
{ {
if (operands[2] == const0_rtx) if (operands[2] == const0_rtx)
return \"and\\t%0, %1, %3, asr #31\"; return \"and\\t%0, %1, %3, asr #31\";
return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\"; return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
} }
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) else if (which_alternative != 0 && REG_P (operands[2]))
{ {
if (operands[1] == const0_rtx) if (operands[1] == const0_rtx)
return \"bic\\t%0, %2, %3, asr #31\"; return \"bic\\t%0, %2, %3, asr #31\";
...@@ -513,13 +513,13 @@ ...@@ -513,13 +513,13 @@
if (GET_CODE (operands[5]) == GE if (GET_CODE (operands[5]) == GE
&& (operands[4] == const0_rtx)) && (operands[4] == const0_rtx))
{ {
if (which_alternative != 1 && GET_CODE (operands[1]) == REG) if (which_alternative != 1 && REG_P (operands[1]))
{ {
if (operands[2] == const0_rtx) if (operands[2] == const0_rtx)
return \"bic\\t%0, %1, %3, asr #31\"; return \"bic\\t%0, %1, %3, asr #31\";
return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\"; return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
} }
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) else if (which_alternative != 0 && REG_P (operands[2]))
{ {
if (operands[1] == const0_rtx) if (operands[1] == const0_rtx)
return \"and\\t%0, %2, %3, asr #31\"; return \"and\\t%0, %2, %3, asr #31\";
...@@ -528,7 +528,7 @@ ...@@ -528,7 +528,7 @@
/* The only case that falls through to here is when both ops 1 & 2 /* The only case that falls through to here is when both ops 1 & 2
are constants. */ are constants. */
} }
if (GET_CODE (operands[4]) == CONST_INT if (CONST_INT_P (operands[4])
&& !const_ok_for_arm (INTVAL (operands[4]))) && !const_ok_for_arm (INTVAL (operands[4])))
output_asm_insn (\"cmn\\t%3, #%n4\", operands); output_asm_insn (\"cmn\\t%3, #%n4\", operands);
else else
...@@ -680,7 +680,7 @@ ...@@ -680,7 +680,7 @@
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed "TARGET_THUMB2 && reload_completed
&& ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT) && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
|| REG_P(operands[2]))" || REG_P (operands[2]))"
"* return arm_output_shift(operands, 2);" "* return arm_output_shift(operands, 2);"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "shift" "1") (set_attr "shift" "1")
...@@ -709,7 +709,7 @@ ...@@ -709,7 +709,7 @@
"* "*
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
val = INTVAL(operands[2]); val = INTVAL(operands[2]);
else else
val = 0; val = 0;
...@@ -773,7 +773,7 @@ ...@@ -773,7 +773,7 @@
"* "*
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
val = INTVAL (operands[2]); val = INTVAL (operands[2]);
else else
val = 0; val = 0;
...@@ -797,7 +797,7 @@ ...@@ -797,7 +797,7 @@
"* "*
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE (operands[1]) == CONST_INT) if (CONST_INT_P (operands[1]))
val = INTVAL (operands[1]); val = INTVAL (operands[1]);
else else
val = 0; val = 0;
......
gcc/config/arm/vec-common.md
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]); operands[1] = force_reg (<MODE>mode, operands[1]);
else if (TARGET_NEON && CONSTANT_P (operands[1])) else if (TARGET_NEON && CONSTANT_P (operands[1]))
{ {
......
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