Skip to content

R
riscv-gcc-1
Commit d3c11974 by H.J. Lu Committed by H.J. Lu
Options

Use proper Intel processor names for -march=/-mtune= 

gcc/

	* config/i386/core2.md: Replace corei7 with nehalem.

	* config/i386/driver-i386.c (host_detect_local_cpu): Use nehalem,
	westmere, sandybridge, ivybridge, haswell, bonnell, silvermont
	for cpu names.

	* config/i386/i386-c.c (ix86_target_macros_internal): Replace
	PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM,
	PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE,
	PROCESSOR_BONNELL, PROCESSOR_SILVERMONT.  Define
	__nehalem/__nehalem__, __sandybridge/__sandybridge__,
	__haswell/__haswell__, __tune_nehalem__, __tune_sandybridge__,
	__tune_haswell__, __bonnell/__bonnell__,
	__silvermont/__silvermont__, __tune_bonnell__,
	__tune_silvermont__.

	* config/i386/i386.c (m_COREI7): Renamed to ...
	(m_NEHALEM): This.
	(m_COREI7_AVX): Renamed to ...
	(m_SANDYBRIDGE): This.
	(m_ATOM): Renamed to ...
	(m_BONNELL): This.
	(m_SLM): Renamed to ...
	(m_SILVERMONT): This.
	(m_CORE_ALL): Updated.
	(cpu_names): Add "nehalem", "westmere", "sandybridge",
	"ivybridge", "haswell", "broadwell", "bonnell", "silvermont".
	(PTA_CORE2): New.
	(PTA_NEHALEM): Likewise.
	(PTA_WESTMERE): Likewise.
	(PTA_SANDYBRIDGE): Likewise.
	(PTA_IVYBRIDGE): Likewise.
	(PTA_HASWELL): Likewise.
	(PTA_BROADWELL): Likewise.
	(PTA_BONNELL): Likewise.
	(PTA_SILVERMONT): Likewise.
	(ix86_option_override_internal): Use new PTA_XXX.  Add nehalem,
	westmere, sandybridge, ivybridge, haswell, bonnell, silvermont.
	(ix86_lea_outperforms): Updated.
	(ix86_issue_rate): Likewise.
	(ix86_adjust_cost): Likewise.
	(ia32_multipass_dfa_lookahead): Likewise.
	(do_reorder_for_imul): Likewise.
	(swap_top_of_ready_list): Likewise.
	(ix86_sched_reorder): Likewise.
	(ix86_sched_init_global): Likewise.
	(get_builtin_code_for_version): Likewise.
	(processor_model): Replace M_INTEL_ATOM, M_INTEL_SLM with
	M_INTEL_BONNELL, M_INTEL_SILVERMONT.
	(arch_names_table): Updated.

	* config/i386/i386.h (TARGET_COREI7): Removed.
	(TARGET_COREI7_AVX): Likewise.
	(TARGET_ATOM): Likewise.
	(TARGET_SLM): Likewise.
	(TARGET_NEHALEM): New.
	(TARGET_SANDYBRIDGE): Likewise.
	(TARGET_BONNELL): Likewise.
	(TARGET_SILVERMONT): Likewise.
	(target_cpu_default): Add TARGET_CPU_DEFAULT_core_avx2,
	TARGET_CPU_DEFAULT_nehalem, TARGET_CPU_DEFAULT_westmere,
	TARGET_CPU_DEFAULT_sandybridge, TARGET_CPU_DEFAULT_ivybridge,
	TARGET_CPU_DEFAULT_broadwell, TARGET_CPU_DEFAULT_bonnell,
	TARGET_CPU_DEFAULT_silvermont.  Move TARGET_CPU_DEFAULT_haswell
	before TARGET_CPU_DEFAULT_broadwell.
	(processor_type): Replace PROCESSOR_COREI7, PROCESSOR_COREI7_AVX,
	PROCESSOR_ATOM, PROCESSOR_SLM with PROCESSOR_NEHALEM,
	PROCESSOR_SANDYBRIDGE, PROCESSOR_BONNELL, PROCESSOR_SILVERMONT.

	* config/i386/i386.md (cpu): Replace corei7 with nehalem.

	* config/i386/x86-tune.def: Updated.

	* doc/invoke.texi: Replace corei7, corei7-avx, core-avx-i,
	core-avx2, atom, slm with nehalem, sandybridge, ivybridge,
	haswell, bonnel, silvermont.  Add westmere.

libgcc/

	* config/i386/cpuinfo.c (processor_subtypes): Replace INTEL_ATOM,
	INTEL_SLM with INTEL_BONNELL, INTEL_SILVERMONT.
	(get_intel_cpu): Updated.

Co-Authored-By: Tocar Ilya <ilya.tocar@intel.com>

From-SVN: r206178
parent ae8310ec
Showing with 249 additions and 124 deletions
gcc/ChangeLog
2013-12-23 H.J. Lu <hongjiu.lu@intel.com>
Tocar Ilya <ilya.tocar@intel.com>
* config/i386/core2.md: Replace corei7 with nehalem.
* config/i386/driver-i386.c (host_detect_local_cpu): Use nehalem,
westmere, sandybridge, ivybridge, haswell, bonnell, silvermont
for cpu names.
* config/i386/i386-c.c (ix86_target_macros_internal): Replace
PROCESSOR_COREI7, PROCESSOR_COREI7_AVX, PROCESSOR_ATOM,
PROCESSOR_SLM with PROCESSOR_NEHALEM, PROCESSOR_SANDYBRIDGE,
PROCESSOR_BONNELL, PROCESSOR_SILVERMONT. Define
__nehalem/__nehalem__, __sandybridge/__sandybridge__,
__haswell/__haswell__, __tune_nehalem__, __tune_sandybridge__,
__tune_haswell__, __bonnell/__bonnell__,
__silvermont/__silvermont__, __tune_bonnell__,
__tune_silvermont__.
* config/i386/i386.c (m_COREI7): Renamed to ...
(m_NEHALEM): This.
(m_COREI7_AVX): Renamed to ...
(m_SANDYBRIDGE): This.
(m_ATOM): Renamed to ...
(m_BONNELL): This.
(m_SLM): Renamed to ...
(m_SILVERMONT): This.
(m_CORE_ALL): Updated.
(cpu_names): Add "nehalem", "westmere", "sandybridge",
"ivybridge", "haswell", "broadwell", "bonnell", "silvermont".
(PTA_CORE2): New.
(PTA_NEHALEM): Likewise.
(PTA_WESTMERE): Likewise.
(PTA_SANDYBRIDGE): Likewise.
(PTA_IVYBRIDGE): Likewise.
(PTA_HASWELL): Likewise.
(PTA_BROADWELL): Likewise.
(PTA_BONNELL): Likewise.
(PTA_SILVERMONT): Likewise.
(ix86_option_override_internal): Use new PTA_XXX. Add nehalem,
westmere, sandybridge, ivybridge, haswell, bonnell, silvermont.
(ix86_lea_outperforms): Updated.
(ix86_issue_rate): Likewise.
(ix86_adjust_cost): Likewise.
(ia32_multipass_dfa_lookahead): Likewise.
(do_reorder_for_imul): Likewise.
(swap_top_of_ready_list): Likewise.
(ix86_sched_reorder): Likewise.
(ix86_sched_init_global): Likewise.
(get_builtin_code_for_version): Likewise.
(processor_model): Replace M_INTEL_ATOM, M_INTEL_SLM with
M_INTEL_BONNELL, M_INTEL_SILVERMONT.
(arch_names_table): Updated.
* config/i386/i386.h (TARGET_COREI7): Removed.
(TARGET_COREI7_AVX): Likewise.
(TARGET_ATOM): Likewise.
(TARGET_SLM): Likewise.
(TARGET_NEHALEM): New.
(TARGET_SANDYBRIDGE): Likewise.
(TARGET_BONNELL): Likewise.
(TARGET_SILVERMONT): Likewise.
(target_cpu_default): Add TARGET_CPU_DEFAULT_core_avx2,
TARGET_CPU_DEFAULT_nehalem, TARGET_CPU_DEFAULT_westmere,
TARGET_CPU_DEFAULT_sandybridge, TARGET_CPU_DEFAULT_ivybridge,
TARGET_CPU_DEFAULT_broadwell, TARGET_CPU_DEFAULT_bonnell,
TARGET_CPU_DEFAULT_silvermont. Move TARGET_CPU_DEFAULT_haswell
before TARGET_CPU_DEFAULT_broadwell.
(processor_type): Replace PROCESSOR_COREI7, PROCESSOR_COREI7_AVX,
PROCESSOR_ATOM, PROCESSOR_SLM with PROCESSOR_NEHALEM,
PROCESSOR_SANDYBRIDGE, PROCESSOR_BONNELL, PROCESSOR_SILVERMONT.
* config/i386/i386.md (cpu): Replace corei7 with nehalem.
* config/i386/x86-tune.def: Updated.
* doc/invoke.texi: Replace corei7, corei7-avx, core-avx-i,
core-avx2, atom, slm with nehalem, sandybridge, ivybridge,
haswell, bonnel, silvermont. Add westmere.
2013-12-23 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/57422
gcc/config/i386/driver-i386.c
......@@ -643,13 +643,13 @@ const char *host_detect_local_cpu (int argc, const char **argv)
{
case 0x1c:
case 0x26:
/* Atom. */
cpu = "atom";
/* Bonnell. */
cpu = "bonnell";
break;
case 0x37:
case 0x4d:
/* Silvermont. */
cpu = "slm";
cpu = "silvermont";
break;
case 0x0f:
/* Merom. */
......@@ -663,27 +663,29 @@ const char *host_detect_local_cpu (int argc, const char **argv)
case 0x1f:
case 0x2e:
/* Nehalem. */
cpu = "nehalem";
break;
case 0x25:
case 0x2c:
case 0x2f:
/* Westmere. */
cpu = "corei7";
cpu = "westmere";
break;
case 0x2a:
case 0x2d:
/* Sandy Bridge. */
cpu = "corei7-avx";
cpu = "sandybridge";
break;
case 0x3a:
case 0x3e:
/* Ivy Bridge. */
cpu = "core-avx-i";
cpu = "ivybridge";
break;
case 0x3c:
case 0x45:
case 0x46:
/* Haswell. */
cpu = "core-avx2";
cpu = "haswell";
break;
default:
if (arch)
......@@ -693,24 +695,24 @@ const char *host_detect_local_cpu (int argc, const char **argv)
cpu = "broadwell";
else if (has_avx2)
/* Assume Haswell. */
cpu = "core-avx2";
cpu = "haswell";
else if (has_avx)
/* Assume Sandy Bridge. */
cpu = "corei7-avx";
cpu = "sandybridge";
else if (has_sse4_2)
{
if (has_movbe)
/* Assume SLM. */
cpu = "slm";
/* Assume Silvermont. */
cpu = "silvermont";
else
/* Assume Core i7. */
cpu = "corei7";
/* Assume Nehalem. */
cpu = "nehalem";
}
else if (has_ssse3)
{
if (has_movbe)
/* Assume Atom. */
cpu = "atom";
/* Assume Bonnell. */
cpu = "bonnell";
else
/* Assume Core 2. */
cpu = "core2";
......
gcc/config/i386/i386-c.c
......@@ -141,25 +141,35 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__core2");
def_or_undef (parse_in, "__core2__");
break;
case PROCESSOR_COREI7:
case PROCESSOR_NEHALEM:
def_or_undef (parse_in, "__corei7");
def_or_undef (parse_in, "__corei7__");
def_or_undef (parse_in, "__nehalem");
def_or_undef (parse_in, "__nehalem__");
break;
case PROCESSOR_COREI7_AVX:
case PROCESSOR_SANDYBRIDGE:
def_or_undef (parse_in, "__corei7_avx");
def_or_undef (parse_in, "__corei7_avx__");
def_or_undef (parse_in, "__sandybridge");
def_or_undef (parse_in, "__sandybridge__");
break;
case PROCESSOR_HASWELL:
def_or_undef (parse_in, "__core_avx2");
def_or_undef (parse_in, "__core_avx2__");
def_or_undef (parse_in, "__haswell");
def_or_undef (parse_in, "__haswell__");
break;
case PROCESSOR_ATOM:
case PROCESSOR_BONNELL:
def_or_undef (parse_in, "__atom");
def_or_undef (parse_in, "__atom__");
def_or_undef (parse_in, "__bonnell");
def_or_undef (parse_in, "__bonnell__");
break;
case PROCESSOR_SLM:
case PROCESSOR_SILVERMONT:
def_or_undef (parse_in, "__slm");
def_or_undef (parse_in, "__slm__");
def_or_undef (parse_in, "__silvermont");
def_or_undef (parse_in, "__silvermont__");
break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
......@@ -246,20 +256,25 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_CORE2:
def_or_undef (parse_in, "__tune_core2__");
break;
case PROCESSOR_COREI7:
case PROCESSOR_NEHALEM:
def_or_undef (parse_in, "__tune_corei7__");
def_or_undef (parse_in, "__tune_nehalem__");
break;
case PROCESSOR_COREI7_AVX:
case PROCESSOR_SANDYBRIDGE:
def_or_undef (parse_in, "__tune_corei7_avx__");
def_or_undef (parse_in, "__tune_sandybridge__");
break;
case PROCESSOR_HASWELL:
def_or_undef (parse_in, "__tune_core_avx2__");
def_or_undef (parse_in, "__tune_haswell__");
break;
case PROCESSOR_ATOM:
case PROCESSOR_BONNELL:
def_or_undef (parse_in, "__tune_atom__");
def_or_undef (parse_in, "__tune_bonnell__");
break;
case PROCESSOR_SLM:
case PROCESSOR_SILVERMONT:
def_or_undef (parse_in, "__tune_slm__");
def_or_undef (parse_in, "__tune_silvermont__");
break;
case PROCESSOR_GENERIC:
break;
......
gcc/config/i386/i386.h
......@@ -301,9 +301,11 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
#define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7)
#define TARGET_COREI7_AVX (ix86_tune == PROCESSOR_COREI7_AVX)
#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
......@@ -312,8 +314,6 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)
#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
#define TARGET_SLM (ix86_tune == PROCESSOR_SLM)
/* Feature tests against the various tunings. */
enum ix86_tune_indices {
......@@ -625,9 +625,17 @@ enum target_cpu_default
TARGET_CPU_DEFAULT_core2,
TARGET_CPU_DEFAULT_corei7,
TARGET_CPU_DEFAULT_corei7_avx,
TARGET_CPU_DEFAULT_haswell,
TARGET_CPU_DEFAULT_core_avx2,
TARGET_CPU_DEFAULT_atom,
TARGET_CPU_DEFAULT_slm,
TARGET_CPU_DEFAULT_nehalem,
TARGET_CPU_DEFAULT_westmere,
TARGET_CPU_DEFAULT_sandybridge,
TARGET_CPU_DEFAULT_ivybridge,
TARGET_CPU_DEFAULT_haswell,
TARGET_CPU_DEFAULT_broadwell,
TARGET_CPU_DEFAULT_bonnell,
TARGET_CPU_DEFAULT_silvermont,
TARGET_CPU_DEFAULT_intel,
TARGET_CPU_DEFAULT_geode,
......@@ -2220,9 +2228,11 @@ enum processor_type
PROCESSOR_K8,
PROCESSOR_NOCONA,
PROCESSOR_CORE2,
PROCESSOR_COREI7,
PROCESSOR_COREI7_AVX,
PROCESSOR_NEHALEM,
PROCESSOR_SANDYBRIDGE,
PROCESSOR_HASWELL,
PROCESSOR_BONNELL,
PROCESSOR_SILVERMONT,
PROCESSOR_GENERIC,
PROCESSOR_AMDFAM10,
PROCESSOR_BDVER1,
......@@ -2231,8 +2241,6 @@ enum processor_type
PROCESSOR_BDVER4,
PROCESSOR_BTVER1,
PROCESSOR_BTVER2,
PROCESSOR_ATOM,
PROCESSOR_SLM,
PROCESSOR_max
};
......
gcc/config/i386/i386.md
......@@ -354,7 +354,7 @@
;; Processor type.
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
atom,slm,generic,amdfam10,bdver1,bdver2,bdver3,bdver4,
btver1,btver2"
(const (symbol_ref "ix86_schedule")))
......
gcc/doc/invoke.texi
......@@ -14648,34 +14648,38 @@ SSE2 and SSE3 instruction set support.
Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
@item corei7
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
@item nehalem
Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2 and POPCNT instruction set support.
@item corei7-avx
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
@item westmere
Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AES and PCLMUL instruction set support.
@item sandybridge
Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
@item core-avx-i
Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
@item ivybridge
Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
instruction set support.
@item core-avx2
Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
@item haswell
Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
BMI, BMI2 and F16C instruction set support.
@item broadwell
Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW instruction set support.
BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
@item atom
Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
@item bonnell
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
instruction set support.
@item slm
@item silvermont
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
......
libgcc/ChangeLog
2013-12-23 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/cpuinfo.c (processor_subtypes): Replace INTEL_ATOM,
INTEL_SLM with INTEL_BONNELL, INTEL_SILVERMONT.
(get_intel_cpu): Updated.
2013-12-12 Zhenqiang Chen <zhenqiang.chen@arm.com>
* config.host (arm*-*-uclinux*): Move t-arm before t-bpabi.
......
libgcc/config/i386/cpuinfo.c
......@@ -56,12 +56,12 @@ enum processor_vendor
enum processor_types
{
INTEL_ATOM = 1,
INTEL_BONNELL = 1,
INTEL_CORE2,
INTEL_COREI7,
AMDFAM10H,
AMDFAM15H,
INTEL_SLM,
INTEL_SILVERMONT,
CPU_TYPE_MAX
};
......@@ -167,13 +167,13 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
{
case 0x1c:
case 0x26:
/* Atom. */
__cpu_model.__cpu_type = INTEL_ATOM;
/* Bonnell. */
__cpu_model.__cpu_type = INTEL_BONNELL;
break;
case 0x37:
case 0x4d:
/* Silvermont. */
__cpu_model.__cpu_type = INTEL_SLM;
__cpu_model.__cpu_type = INTEL_SILVERMONT;
break;
case 0x1a:
case 0x1e:
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment