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Commit d371df6f by Joseph Myers Committed by Joseph Myers
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gcc_update (gcc/config/mips/mips-tables.opt): New dependencies. 

contrib:
	* gcc_update (gcc/config/mips/mips-tables.opt): New dependencies.

gcc:
	* config/mips/genopt.sh, config/mips/mips-cpus.def: New files.
	* config/mips/mips-tables.opt: New file (generated).
	* config.gcc (mips*-*-*): Add mips/mips-tables.opt to
	extra_options.
	* config/mips/mips-opts.h (MIPS_ARCH_OPTION_FROM_ABI,
	MIPS_ARCH_OPTION_NATIVE): Define.
	* config/mips/mips.c (mips_cpu_info_table): Move contents to
	mips-cpus.def.
	(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p,
	mips_parse_cpu): Remove.
	(mips_cpu_info_from_opt, mips_default_arch): New.
	(mips_handle_option): Don't assert that global structures are in
	use.  Don't handle OPT_march_, OPT_mtune_ and OPT_mips here.
	(mips_option_override): Use new variables and functions to set
	state of these options.  Use strcmp to check for individual CPU
	names.
	* config/mips/mips.h (MIPS_CPU_STRING_DEFAULT): Remove default
	definition.
	* config/mips/mips.opt (march=): Use ToLower and Enum.
	(mips): Use ToLower, Enum and Var.
	(mtune=): Use ToLower and Enum.
	* config/mips/t-mips ($(srcdir)/config/mips/mips-tables.opt): New.

From-SVN: r173561
parent 4fc07af9
Showing with 316 additions and 12 deletions
contrib/ChangeLog
2011-05-09 Joseph Myers <joseph@codesourcery.com>
* gcc_update (gcc/config/mips/mips-tables.opt): New dependencies.
2010-05-05 Joern Rennecke <joern.rennecke@embecosm.com>
* config-list.mk: New file.
......
contrib/gcc_update
......@@ -82,6 +82,7 @@ gcc/fixinc/fixincl.x: gcc/fixinc/fixincl.tpl gcc/fixinc/inclhack.def
gcc/config/arm/arm-tune.md: gcc/config/arm/arm-cores.def gcc/config/arm/gentune.sh
gcc/config/arm/arm-tables.opt: gcc/config/arm/arm-arches.def gcc/config/arm/arm-cores.def gcc/config/arm/genopt.sh
gcc/config/m68k/m68k-tables.opt: gcc/config/m68k/m68k-devices.def gcc/config/m68k/m68k-isas.def gcc/config/m68k/m68k-microarchs.def gcc/config/m68k/genopt.sh
gcc/config/mips/mips-tables.opt: gcc/config/mips/mips-cpus.def gcc/config/mips/genopt.sh
# And then, language-specific files
gcc/cp/cfns.h: gcc/cp/cfns.gperf
gcc/java/keyword.h: gcc/java/keyword.gperf
......
gcc/ChangeLog
2011-05-09 Joseph Myers <joseph@codesourcery.com>
* config/mips/genopt.sh, config/mips/mips-cpus.def: New files.
* config/mips/mips-tables.opt: New file (generated).
* config.gcc (mips*-*-*): Add mips/mips-tables.opt to
extra_options.
* config/mips/mips-opts.h (MIPS_ARCH_OPTION_FROM_ABI,
MIPS_ARCH_OPTION_NATIVE): Define.
* config/mips/mips.c (mips_cpu_info_table): Move contents to
mips-cpus.def.
(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p,
mips_parse_cpu): Remove.
(mips_cpu_info_from_opt, mips_default_arch): New.
(mips_handle_option): Don't assert that global structures are in
use. Don't handle OPT_march_, OPT_mtune_ and OPT_mips here.
(mips_option_override): Use new variables and functions to set
state of these options. Use strcmp to check for individual CPU
names.
* config/mips/mips.h (MIPS_CPU_STRING_DEFAULT): Remove default
definition.
* config/mips/mips.opt (march=): Use ToLower and Enum.
(mips): Use ToLower, Enum and Var.
(mtune=): Use ToLower and Enum.
* config/mips/t-mips ($(srcdir)/config/mips/mips-tables.opt): New.
2011-05-08 Jan Hubicka <jh@suse.cz>
* gimple.c (type_pair_hash, type_pair_eq, lookup_type_pair):
......
gcc/config.gcc
......@@ -371,7 +371,7 @@ mips*-*-*)
cpu_type=mips
need_64bit_hwint=yes
extra_headers="loongson.h"
extra_options="${extra_options} g.opt"
extra_options="${extra_options} g.opt mips/mips-tables.opt"
;;
picochip-*-*)
cpu_type=picochip
......
gcc/config/mips/genopt.sh 0 → 100755
#!/bin/sh
# Generate mips-tables.opt from the list of CPUs in mips-cpus.def.
# Copyright (C) 2011 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
cat <<EOF
; -*- buffer-read-only: t -*-
; Generated automatically by genopt.sh from mips-cpus.def.
; Copyright (C) 2011 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
Enum
Name(mips_arch_opt_value) Type(int)
Known MIPS CPUs (for use with the -march= and -mtune= options):
Enum
Name(mips_mips_opt_value) Type(int)
Known MIPS ISA levels (for use with the -mips option):
EnumValue
Enum(mips_arch_opt_value) String(from-abi) Value(MIPS_ARCH_OPTION_FROM_ABI)
EnumValue
Enum(mips_arch_opt_value) String(native) Value(MIPS_ARCH_OPTION_NATIVE) DriverOnly
EOF
awk -F'[(, ]+' '
BEGIN {
value = 0
}
# Write an entry for a single string accepted as a -march= argument.
function write_one_arch_value(name, value, flags)
{
print "EnumValue"
print "Enum(mips_arch_opt_value) String(" name ") Value(" value ")" flags
print ""
if (name ~ "^mips") {
sub("^mips", "", name)
print "EnumValue"
print "Enum(mips_mips_opt_value) String(" name ") Value(" value ")"
print ""
}
}
# The logic for matching CPU name variants should be the same as in GAS.
# Write an entry for a single string accepted as a -march= argument,
# plus any variant with a final "000" replaced by "k".
function write_arch_value_maybe_k(name, value, flags)
{
write_one_arch_value(name, value, flags)
if (name ~ "000$") {
sub("000$", "k", name)
write_one_arch_value(name, value, "")
}
}
# Write all the entries for a -march= argument. In addition to
# replacement of a final "000" with "k", an argument starting with
# "vr", "rm" or "r" followed by a number, or just a plain number,
# matches a plain number or "r" followed by a plain number.
function write_all_arch_values(name, value)
{
write_arch_value_maybe_k(name, value, " Canonical")
cname = name
if (cname ~ "^vr") {
sub("^vr", "", cname)
} else if (cname ~ "^rm") {
sub("^rm", "", cname)
} else if (cname ~ "^r") {
sub("^r", "", cname)
}
if (cname ~ "^[0-9]") {
if (cname != name)
write_arch_value_maybe_k(cname, value, "")
rname = "r" cname
if (rname != name)
write_arch_value_maybe_k(rname, value, "")
}
}
/^MIPS_CPU/ {
name = $2
gsub("\"", "", name)
write_all_arch_values(name, value)
value++
}' $1/mips-cpus.def
gcc/config/mips/mips-cpus.def 0 → 100644
/* MIPS CPU names.
Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
2011
Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* A table describing all the processors GCC knows about. The first
mention of an ISA level is taken as the canonical name for that
ISA.
To ease comparison, please keep this table in the same order
as GAS's mips_cpu_info_table. Please also make sure that
MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
options correctly.
Before including this file, define a macro:
MIPS_CPU (NAME, CPU, ISA, FLAGS)
where the arguments are the fields of struct mips_cpu_info. */
/* Entries for generic ISAs. */
MIPS_CPU ("mips1", PROCESSOR_R3000, 1, 0)
MIPS_CPU ("mips2", PROCESSOR_R6000, 2, 0)
MIPS_CPU ("mips3", PROCESSOR_R4000, 3, 0)
MIPS_CPU ("mips4", PROCESSOR_R8000, 4, 0)
/* Prefer not to use branch-likely instructions for generic MIPS32rX
and MIPS64rX code. The instructions were officially deprecated
in revisions 2 and earlier, but revision 3 is likely to downgrade
that to a recommendation to avoid the instructions in code that
isn't tuned to a specific processor. */
MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY)
/* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
/* MIPS I processors. */
MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
/* MIPS II processors. */
MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
/* MIPS III processors. */
MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
MIPS_CPU ("vr4100", PROCESSOR_R4100, 3, 0)
MIPS_CPU ("vr4111", PROCESSOR_R4111, 3, 0)
MIPS_CPU ("vr4120", PROCESSOR_R4120, 3, 0)
MIPS_CPU ("vr4130", PROCESSOR_R4130, 3, 0)
MIPS_CPU ("vr4300", PROCESSOR_R4300, 3, 0)
MIPS_CPU ("r4400", PROCESSOR_R4000, 3, 0)
MIPS_CPU ("r4600", PROCESSOR_R4600, 3, 0)
MIPS_CPU ("orion", PROCESSOR_R4600, 3, 0)
MIPS_CPU ("r4650", PROCESSOR_R4650, 3, 0)
/* ST Loongson 2E/2F processors. */
MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY)
/* MIPS IV processors. */
MIPS_CPU ("r8000", PROCESSOR_R8000, 4, 0)
MIPS_CPU ("r10000", PROCESSOR_R10000, 4, 0)
MIPS_CPU ("r12000", PROCESSOR_R10000, 4, 0)
MIPS_CPU ("r14000", PROCESSOR_R10000, 4, 0)
MIPS_CPU ("r16000", PROCESSOR_R10000, 4, 0)
MIPS_CPU ("vr5000", PROCESSOR_R5000, 4, 0)
MIPS_CPU ("vr5400", PROCESSOR_R5400, 4, 0)
MIPS_CPU ("vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("rm7000", PROCESSOR_R7000, 4, 0)
MIPS_CPU ("rm9000", PROCESSOR_R9000, 4, 0)
/* MIPS32 processors. */
MIPS_CPU ("4kc", PROCESSOR_4KC, 32, 0)
MIPS_CPU ("4km", PROCESSOR_4KC, 32, 0)
MIPS_CPU ("4kp", PROCESSOR_4KP, 32, 0)
MIPS_CPU ("4ksc", PROCESSOR_4KC, 32, 0)
/* MIPS32 Release 2 processors. */
MIPS_CPU ("m4k", PROCESSOR_M4K, 33, 0)
MIPS_CPU ("4kec", PROCESSOR_4KC, 33, 0)
MIPS_CPU ("4kem", PROCESSOR_4KC, 33, 0)
MIPS_CPU ("4kep", PROCESSOR_4KP, 33, 0)
MIPS_CPU ("4ksd", PROCESSOR_4KC, 33, 0)
MIPS_CPU ("24kc", PROCESSOR_24KC, 33, 0)
MIPS_CPU ("24kf2_1", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("24kf", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("24kf1_1", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("24kfx", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("24kx", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("24kec", PROCESSOR_24KC, 33, 0) /* 24K with DSP. */
MIPS_CPU ("24kef2_1", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("24kef", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("24kef1_1", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("24kefx", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("24kex", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("34kc", PROCESSOR_24KC, 33, 0) /* 34K with MT/DSP. */
MIPS_CPU ("34kf2_1", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("34kf", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("34kf1_1", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0)
MIPS_CPU ("74kc", PROCESSOR_74KC, 33, 0) /* 74K with DSPr2. */
MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, 0)
MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, 0)
MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, 0)
MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, 0)
MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, 0)
MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, 0)
MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP. */
MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, 33, 0)
MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0)
/* MIPS64 processors. */
MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0)
MIPS_CPU ("5kf", PROCESSOR_5KF, 64, 0)
MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("xlr", PROCESSOR_XLR, 64, 0)
MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
/* MIPS64 Release 2 processors. */
MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
gcc/config/mips/mips-opts.h
......@@ -36,4 +36,10 @@ enum mips_r10k_cache_barrier_setting {
R10K_CACHE_BARRIER_LOAD_STORE
};
/* No enumeration is defined to index the -march= values (entries in
mips_cpu_info_table), with the type int being used instead, but we
need to distinguish the special "from-abi" and "native" values. */
#define MIPS_ARCH_OPTION_FROM_ABI -1
#define MIPS_ARCH_OPTION_NATIVE -2
#endif
gcc/config/mips/mips.h
......@@ -572,13 +572,6 @@ struct mips_cpu_info {
#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
#endif
/* 'from-abi' makes a good default: you get whatever the ABI requires. */
#ifndef MIPS_ISA_DEFAULT
#ifndef MIPS_CPU_STRING_DEFAULT
#define MIPS_CPU_STRING_DEFAULT "from-abi"
#endif
#endif
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
/* Make this compile time constant for libgcc2 */
......
gcc/config/mips/mips.opt
......@@ -59,7 +59,7 @@ Target Report Var(TARGET_MAD)
Use PMC-style 'mad' instructions
march=
Target RejectNegative Joined Var(mips_arch_string)
Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value)
-march=ISA Generate code for the given ISA
mbranch-cost=
......@@ -222,7 +222,7 @@ Target Report Var(TARGET_INTERLINK_MIPS16) Init(0)
Generate code that can be safely linked with MIPS16 code.
mips
Target RejectNegative Joined
Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
-mipsN Generate code for ISA level N
mips16
......@@ -339,7 +339,7 @@ Target Report Mask(SYNCI)
Use synci instruction to invalidate i-cache
mtune=
Target RejectNegative Joined Var(mips_tune_string)
Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
-mtune=PROCESSOR Optimize the output for PROCESSOR
muninit-const-in-rodata
......
gcc/config/mips/t-mips
# Copyright (C) 2002, 2003, 2006 Free Software Foundation, Inc.
# Copyright (C) 2002, 2003, 2006, 2011 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
......@@ -39,3 +39,8 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
LIB2_SIDITI_CONV_FUNCS=yes
$(srcdir)/config/mips/mips-tables.opt: $(srcdir)/config/mips/genopt.sh \
$(srcdir)/config/mips/mips-cpus.def
$(SHELL) $(srcdir)/config/mips/genopt.sh $(srcdir)/config/mips > \
$(srcdir)/config/mips/mips-tables.opt
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