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Commit d33e32a7 by Jakub Jelinek Committed by Jakub Jelinek
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re PR target/83604 (ICE in copy_to_mode_reg, at explow.c:630) 

	PR target/83604
	* config/i386/sse.md (VI248_VLBW): Rename to ...
	(VI248_AVX512VL): ... this.  Don't guard V32HI with TARGET_AVX512BW.
	(vpshrd_<mode><mask_name>, vpshld_<mode><mask_name>,
	vpshrdv_<mode>, vpshrdv_<mode>_mask, vpshrdv_<mode>_maskz,
	vpshrdv_<mode>_maskz_1, vpshldv_<mode>, vpshldv_<mode>_mask,
	vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1): Use VI248_AVX512VL
	mode iterator instead of VI248_VLBW.

	* gcc.target/i386/pr83604.c: New test.

From-SVN: r256280
parent 3b2a6901
Showing with 81 additions and 54 deletions
gcc/ChangeLog
2018-01-05 Jakub Jelinek <jakub@redhat.com>
PR target/83604
* config/i386/sse.md (VI248_VLBW): Rename to ...
(VI248_AVX512VL): ... this. Don't guard V32HI with TARGET_AVX512BW.
(vpshrd_<mode><mask_name>, vpshld_<mode><mask_name>,
vpshrdv_<mode>, vpshrdv_<mode>_mask, vpshrdv_<mode>_maskz,
vpshrdv_<mode>_maskz_1, vpshldv_<mode>, vpshldv_<mode>_mask,
vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1): Use VI248_AVX512VL
mode iterator instead of VI248_VLBW.
2018-01-05 Jan Hubicka <hubicka@ucw.cz> 2018-01-05 Jan Hubicka <hubicka@ucw.cz>
* ipa-fnsummary.c (record_modified_bb_info): Add OP. * ipa-fnsummary.c (record_modified_bb_info): Add OP.
......
gcc/config/i386/sse.md
...@@ -448,8 +448,8 @@ ...@@ -448,8 +448,8 @@
(define_mode_iterator VI2_AVX2_AVX512BW (define_mode_iterator VI2_AVX2_AVX512BW
[(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI])
(define_mode_iterator VI248_VLBW (define_mode_iterator VI248_AVX512VL
[(V32HI "TARGET_AVX512BW") V16SI V8DI [V32HI V16SI V8DI
(V16HI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL")
(V4DI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")
(V4SI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (V4SI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
...@@ -20116,10 +20116,10 @@ ...@@ -20116,10 +20116,10 @@
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshrd_<mode><mask_name>" (define_insn "vpshrd_<mode><mask_name>"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "v") [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
(match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_255_operand" "n")] (match_operand:SI 3 "const_0_to_255_operand" "n")]
UNSPEC_VPSHRD))] UNSPEC_VPSHRD))]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
...@@ -20127,10 +20127,10 @@ ...@@ -20127,10 +20127,10 @@
[(set_attr ("prefix") ("evex"))]) [(set_attr ("prefix") ("evex"))])
(define_insn "vpshld_<mode><mask_name>" (define_insn "vpshld_<mode><mask_name>"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "v") [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
(match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_255_operand" "n")] (match_operand:SI 3 "const_0_to_255_operand" "n")]
UNSPEC_VPSHLD))] UNSPEC_VPSHLD))]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
...@@ -20138,11 +20138,11 @@ ...@@ -20138,11 +20138,11 @@
[(set_attr ("prefix") ("evex"))]) [(set_attr ("prefix") ("evex"))])
(define_insn "vpshrdv_<mode>" (define_insn "vpshrdv_<mode>"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "0") [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHRDV))] UNSPEC_VPSHRDV))]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
"vpshrdv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }" "vpshrdv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
...@@ -20150,12 +20150,12 @@ ...@@ -20150,12 +20150,12 @@
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshrdv_<mode>_mask" (define_insn "vpshrdv_<mode>_mask"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI248_VLBW (vec_merge:VI248_AVX512VL
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "0") [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHRDV) UNSPEC_VPSHRDV)
(match_dup 1) (match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
...@@ -20165,10 +20165,10 @@ ...@@ -20165,10 +20165,10 @@
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_expand "vpshrdv_<mode>_maskz" (define_expand "vpshrdv_<mode>_maskz"
[(match_operand:VI248_VLBW 0 "register_operand") [(match_operand:VI248_AVX512VL 0 "register_operand")
(match_operand:VI248_VLBW 1 "register_operand") (match_operand:VI248_AVX512VL 1 "register_operand")
(match_operand:VI248_VLBW 2 "register_operand") (match_operand:VI248_AVX512VL 2 "register_operand")
(match_operand:VI248_VLBW 3 "nonimmediate_operand") (match_operand:VI248_AVX512VL 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")] (match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
{ {
...@@ -20180,14 +20180,14 @@ ...@@ -20180,14 +20180,14 @@
}) })
(define_insn "vpshrdv_<mode>_maskz_1" (define_insn "vpshrdv_<mode>_maskz_1"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI248_VLBW (vec_merge:VI248_AVX512VL
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "0") [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHRDV) UNSPEC_VPSHRDV)
(match_operand:VI248_VLBW 4 "const0_operand" "C") (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))] (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
"vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
...@@ -20195,11 +20195,11 @@ ...@@ -20195,11 +20195,11 @@
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshldv_<mode>" (define_insn "vpshldv_<mode>"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "0") [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHLDV))] UNSPEC_VPSHLDV))]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
"vpshldv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }" "vpshldv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
...@@ -20207,12 +20207,12 @@ ...@@ -20207,12 +20207,12 @@
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshldv_<mode>_mask" (define_insn "vpshldv_<mode>_mask"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI248_VLBW (vec_merge:VI248_AVX512VL
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "0") [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHLDV) UNSPEC_VPSHLDV)
(match_dup 1) (match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
...@@ -20222,10 +20222,10 @@ ...@@ -20222,10 +20222,10 @@
(set_attr "mode" "<sseinsnmode>")]) (set_attr "mode" "<sseinsnmode>")])
(define_expand "vpshldv_<mode>_maskz" (define_expand "vpshldv_<mode>_maskz"
[(match_operand:VI248_VLBW 0 "register_operand") [(match_operand:VI248_AVX512VL 0 "register_operand")
(match_operand:VI248_VLBW 1 "register_operand") (match_operand:VI248_AVX512VL 1 "register_operand")
(match_operand:VI248_VLBW 2 "register_operand") (match_operand:VI248_AVX512VL 2 "register_operand")
(match_operand:VI248_VLBW 3 "nonimmediate_operand") (match_operand:VI248_AVX512VL 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")] (match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
{ {
...@@ -20237,14 +20237,14 @@ ...@@ -20237,14 +20237,14 @@
}) })
(define_insn "vpshldv_<mode>_maskz_1" (define_insn "vpshldv_<mode>_maskz_1"
[(set (match_operand:VI248_VLBW 0 "register_operand" "=v") [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI248_VLBW (vec_merge:VI248_AVX512VL
(unspec:VI248_VLBW (unspec:VI248_AVX512VL
[(match_operand:VI248_VLBW 1 "register_operand" "0") [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
(match_operand:VI248_VLBW 2 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "register_operand" "v")
(match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHLDV) UNSPEC_VPSHLDV)
(match_operand:VI248_VLBW 4 "const0_operand" "C") (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))] (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512VBMI2" "TARGET_AVX512VBMI2"
"vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
......
gcc/testsuite/ChangeLog
2018-01-05 Jakub Jelinek <jakub@redhat.com>
PR target/83604
* gcc.target/i386/pr83604.c: New test.
2018-01-05 Richard Sandiford <richard.sandiford@linaro.org> 2018-01-05 Richard Sandiford <richard.sandiford@linaro.org>
* gcc.dg/vect/vect-align-4.c: New test. * gcc.dg/vect/vect-align-4.c: New test.
......
gcc/testsuite/gcc.target/i386/pr83604.c 0 → 100644
/* PR target/83604 */
/* { dg-do compile } */
/* { dg-options "-O2 -mno-avx" } */
typedef short V __attribute__((__vector_size__(64)));
__attribute__((target ("avx512vbmi2"))) V
foo (V x, V y, V z)
{
return __builtin_ia32_vpshrdv_v32hi (x, y, z);
}
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