mips.c (mips_reg_names): Change hilo entry to "".

	* config/mips/mips.c (mips_reg_names): Change hilo entry to "".
	(mips_sw_reg_names): Likewise.
	(mips_regno_to_class): Change hilo entry to NO_REGS.
	(hilo_operand): Use MD_REG_P.
	(extend_operator): New predicate.
	(override_options): Remove 'a' constraint.
	(mips_secondary_reload_class): Remove hilo handling.  Also remove
	handling of (plus sp reg) reloads for mips16.
	(mips_register_move_cost): Remove hilo handling.
	* config/mips/mips.h (FIXED_REGISTERS): Make hilo entry fixed.
	(MD_REG_LAST): Remove hilo from range.
	(HILO_REGNUM): Delete.
	(reg_class): Remove HILO_REG and HILO_AND_GR_REGS.
	(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
	(PREDICATE_CODES): Add entry for extend_operator.
	(DEBUG_REGISTER_NAMES): Change hilo entry to "".
	* config/mips/mips.md: Remove hilo clobbers wherever they occur.
	Remove constraints from multiplication define_expands.  Remove
	clobbers from "decorative" define_expand patterns.
	(UNSPEC_HILO_DELAY): Delete.
	(*mul_acc_si, *mul_sub_si): Add early-clobber to operand 6.
	(mulsidi3, umulsidi3): Change pattern to match the TARGET_64BIT case.
	Adjust C code to just emit insns for !TARGET_64BIT.
	(mulsidi3_internal): Rename to mulsidi3_32bit.
	(mulsidi3_64bit): Use a "d" constraint for the destination.
	Use extend_operator so that the pattern can handle umulsidi3 as well.
	Split the instruction after reload.
	(*mulsidi3_64bit_parts): New pattern, generated by mulsidi3_64bit.
	(umulsidi3_internal): Rename to umulsidi3_32bit.
	(umulsidi3_64bit): Remove.
	(*smsac_di, *umsac_di): Line-wrap fixes.
	(udivsi3_internal): Don't allow operand 2 to be constant.
	(udivdi3_internal, umodsi3_internal, umoddi3_internal): Likewise.
	(movdi_internal2, movsi_internal): Remove hilo alternatives.
	(reload_in[sd]i, reload_out[sd]i, hilo_delay): Remove.

From-SVN: r67654

gcc/ChangeLog

 2003-06-09  Richard Sandiford  <rsandifo@redhat.com>
 
+	* config/mips/mips.c (mips_reg_names): Change hilo entry to "".
+	(mips_sw_reg_names): Likewise.
+	(mips_regno_to_class): Change hilo entry to NO_REGS.
+	(hilo_operand): Use MD_REG_P.
+	(extend_operator): New predicate.
+	(override_options): Remove 'a' constraint.
+	(mips_secondary_reload_class): Remove hilo handling.  Also remove
+	handling of (plus sp reg) reloads for mips16.
+	(mips_register_move_cost): Remove hilo handling.
+	* config/mips/mips.h (FIXED_REGISTERS): Make hilo entry fixed.
+	(MD_REG_LAST): Remove hilo from range.
+	(HILO_REGNUM): Delete.
+	(reg_class): Remove HILO_REG and HILO_AND_GR_REGS.
+	(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
+	(PREDICATE_CODES): Add entry for extend_operator.
+	(DEBUG_REGISTER_NAMES): Change hilo entry to "".
+	* config/mips/mips.md: Remove hilo clobbers wherever they occur.
+	Remove constraints from multiplication define_expands.  Remove
+	clobbers from "decorative" define_expand patterns.
+	(UNSPEC_HILO_DELAY): Delete.
+	(*mul_acc_si, *mul_sub_si): Add early-clobber to operand 6.
+	(mulsidi3, umulsidi3): Change pattern to match the TARGET_64BIT case.
+	Adjust C code to just emit insns for !TARGET_64BIT.
+	(mulsidi3_internal): Rename to mulsidi3_32bit.
+	(mulsidi3_64bit): Use a "d" constraint for the destination.
+	Use extend_operator so that the pattern can handle umulsidi3 as well.
+	Split the instruction after reload.
+	(*mulsidi3_64bit_parts): New pattern, generated by mulsidi3_64bit.
+	(umulsidi3_internal): Rename to umulsidi3_32bit.
+	(umulsidi3_64bit): Remove.
+	(*smsac_di, *umsac_di): Line-wrap fixes.
+	(udivsi3_internal): Don't allow operand 2 to be constant.
+	(udivdi3_internal, umodsi3_internal, umoddi3_internal): Likewise.
+	(movdi_internal2, movsi_internal): Remove hilo alternatives.
+	(reload_in[sd]i, reload_out[sd]i, hilo_delay): Remove.
+
+2003-06-09  Richard Sandiford  <rsandifo@redhat.com>
+
 	PR target/10913
 	* config/mips/mips.h (TARGET_FILE_SWITCHING, NO_DBX_FUNCTION_END,
 	PUT_SDB_SCL, PUT_SDB_INT_VAL, PUT_SDB_VAL, PUT_SDB_ENDEF,

gcc/config/mips/mips.c

@@ -592,7 +592,7 @@ char mips_reg_names[][8] =
  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
- "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
+ "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
  "$fcc5","$fcc6","$fcc7","", "",     "",     "",     "",
  "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
  "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
@@ -621,7 +621,7 @@ char mips_sw_reg_names[][8] =
   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
-  "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
+  "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
   "$fcc5","$fcc6","$fcc7","$rap", "",     "",     "",     "",
   "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
   "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
@@ -656,7 +656,7 @@ const enum reg_class mips_regno_to_class[] =
   FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
   FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
   FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  HI_REG,	LO_REG,		HILO_REG,	ST_REGS,
+  HI_REG,	LO_REG,		NO_REGS,	ST_REGS,
   ST_REGS,	ST_REGS,	ST_REGS,	ST_REGS,
   ST_REGS,	ST_REGS,	ST_REGS,	NO_REGS,
   NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
@@ -1518,8 +1518,18 @@ hilo_operand (op, mode)
      enum machine_mode mode;
 {
   return ((mode == VOIDmode || mode == GET_MODE (op))
-	  && REG_P (op)
-	  && (REGNO (op) == HI_REGNUM || REGNO (op) == LO_REGNUM));
+	  && REG_P (op) && MD_REG_P (REGNO (op)));
+}
+
+/* Return true if OP is an extension operator.  */
+
+int
+extend_operator (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return ((mode == VOIDmode || mode == GET_MODE (op))
+	  && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
 }
 
 /* Return nonzero if the code of this rtx pattern is EQ or NE.  */
@@ -5555,7 +5565,6 @@ override_options ()
   mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
   mips_char_to_class['h'] = HI_REG;
   mips_char_to_class['l'] = LO_REG;
-  mips_char_to_class['a'] = HILO_REG;
   mips_char_to_class['x'] = MD_REGS;
   mips_char_to_class['b'] = ALL_REGS;
   mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
@@ -8541,20 +8550,6 @@ mips_secondary_reload_class (class, mode, x, in_p)
       && DANGEROUS_FOR_LA25_P (x))
     return LEA_REGS;
 
-  /* We always require a general register when copying anything to
-     HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
-     to a general register, or when copying from register 0.  */
-  if (class == HILO_REG && regno != GP_REG_FIRST + 0)
-    return ((! in_p
-	     && gp_reg_p
-	     && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
-	    ? NO_REGS : gr_regs);
-  else if (regno == HILO_REGNUM)
-    return ((in_p
-	     && class == gr_regs
-	     && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
-	    ? NO_REGS : gr_regs);
-
   /* Copying from HI or LO to anywhere other than a general register
      requires a general register.  */
   if (class == HI_REG || class == LO_REG || class == MD_REGS)
@@ -8636,19 +8631,6 @@ mips_secondary_reload_class (class, mode, x, in_p)
 	}
       if (! gp_reg_p)
 	{
-	  /* The stack pointer isn't a valid operand to an add instruction,
-	     so we need to load it into M16_REGS first.  This can happen as
-	     a result of register elimination and form_sum converting
-	     (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST).  We
-	     need an extra register if the dest is the same as the other
-	     register.  In that case, we can't fix the problem by loading SP
-	     into the dest first.  */
-	  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
-	      && GET_CODE (XEXP (x, 1)) == REG
-	      && (XEXP (x, 0) == stack_pointer_rtx
-		  || XEXP (x, 1) == stack_pointer_rtx))
-	    return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
-
 	  if (class == M16_REGS || class == M16_NA_REGS)
 	    return NO_REGS;
 	  return M16_REGS;
@@ -9775,10 +9757,10 @@ mips_reorg ()
    should do this if the `movM' pattern's constraints do not allow
    such copying.
 
-   ??? We make make the cost of moving from HI/LO/HILO/MD into general
+   ??? We make the cost of moving from HI/LO into general
    registers the same as for one of moving general registers to
-   HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
-   pseudo to HI/LO/HILO/MD.  This might hurt optimizations though, it
+   HI/LO for TARGET_MIPS16 in order to prevent allocating a
+   pseudo to HI/LO.  This might hurt optimizations though, it
    isn't clear if it is wise.  And it might not work in all cases.  We
    could solve the DImode LO reg problem by using a multiply, just
    like reload_{in,out}si.  We could solve the SImode/HImode HI reg
@@ -9813,8 +9795,7 @@ mips_register_move_cost (mode, to, from)
 	}
       else if (to == FP_REGS)
 	return 4;
-      else if (to == HI_REG || to == LO_REG || to == MD_REGS
-	       || to == HILO_REG)
+      else if (to == HI_REG || to == LO_REG || to == MD_REGS)
 	{
 	  if (TARGET_MIPS16)
 	    return 12;
@@ -9835,8 +9816,7 @@ mips_register_move_cost (mode, to, from)
       else if (to == ST_REGS)
 	return 8;
     }  /* from == FP_REGS */
-  else if (from == HI_REG || from == LO_REG || from == MD_REGS
-	   || from == HILO_REG)
+  else if (from == HI_REG || from == LO_REG || from == MD_REGS)
     {
       if (GR_REG_CLASS_P (to))
 	{

gcc/config/mips/mips.h

@@ -1683,14 +1683,9 @@ do {							\
 
    On the Mips, we have 32 integer registers, 32 floating point
    registers, 8 condition code registers, and the special registers
-   hi, lo, hilo, and rap.  Afetr that we have 32 COP0 registers, 32
-   COP2 registers, and 32 COp3 registers.  (COP1 is the floating-point
-   processor.)  The 8 condition code registers are only used if
-   mips_isa >= 4.  The hilo register is only used in 64 bit mode.  It
-   represents a 64 bit value stored as two 32 bit values in the hi and
-   lo registers; this is the result of the mult instruction.  rap is a
-   pointer to the stack where the return address reg ($31) was stored.
-   This is needed for C++ exception handling.  */
+   hi and lo.  After that we have 32 COP0 registers, 32 COP2 registers,
+   and 32 COP3 registers.  (COP1 is the floating-point processor.)
+   The 8 condition code registers are only used if mips_isa >= 4.  */
 
 #define FIRST_PSEUDO_REGISTER 176
 
@@ -1711,7 +1706,7 @@ do {							\
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,			\
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,			\
+  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,			\
   /* COP0 registers */							\
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
@@ -1795,7 +1790,7 @@ do {							\
 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
 
 #define MD_REG_FIRST 64
-#define MD_REG_LAST  66
+#define MD_REG_LAST  65
 #define MD_REG_NUM   (MD_REG_LAST - MD_REG_FIRST + 1)
 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
 
@@ -1822,7 +1817,6 @@ do {							\
 #define AT_REGNUM	(GP_REG_FIRST + 1)
 #define HI_REGNUM	(MD_REG_FIRST + 0)
 #define LO_REGNUM	(MD_REG_FIRST + 1)
-#define HILO_REGNUM	(MD_REG_FIRST + 2)
 
 /* FPSW_REGNUM is the single condition code used if mips_isa < 4.  If
    mips_isa >= 4, it should not be used, and an arbitrary ST_REG
@@ -2002,14 +1996,12 @@ enum reg_class
   FP_REGS,			/* floating point registers */
   HI_REG,			/* hi register */
   LO_REG,			/* lo register */
-  HILO_REG,			/* hilo register pair for 64 bit mode mult */
   MD_REGS,			/* multiply/divide registers (hi/lo) */
   COP0_REGS,			/* generic coprocessor classes */
   COP2_REGS,
   COP3_REGS,
   HI_AND_GR_REGS,		/* union classes */
   LO_AND_GR_REGS,
-  HILO_AND_GR_REGS,
   HI_AND_FP_REGS,
   COP0_AND_GR_REGS,
   COP2_AND_GR_REGS,
@@ -2042,7 +2034,6 @@ enum reg_class
   "FP_REGS",								\
   "HI_REG",								\
   "LO_REG",								\
-  "HILO_REG",								\
   "MD_REGS",								\
   /* coprocessor registers */						\
   "COP0_REGS",								\
@@ -2050,7 +2041,6 @@ enum reg_class
   "COP3_REGS",								\
   "HI_AND_GR_REGS",							\
   "LO_AND_GR_REGS",							\
-  "HILO_AND_GR_REGS",							\
   "HI_AND_FP_REGS",							\
   "COP0_AND_GR_REGS",							\
   "COP2_AND_GR_REGS",							\
@@ -2085,14 +2075,12 @@ enum reg_class
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* floating registers*/	\
   { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },	/* hi register */	\
   { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },	/* lo register */	\
-  { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 },	/* hilo register */	\
   { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 },	/* mul/div registers */	\
   { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
   { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
   { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
   { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },	/* union classes */     \
   { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },				\
-  { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 },				\
   { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },				\
   { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 },			\
   { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 },	\
@@ -2186,7 +2174,6 @@ extern const enum reg_class mips_regno_to_class[];
    'h'	Hi register
    'l'	Lo register
    'x'	Multiply/divide registers
-   'a'	HILO_REG
    'z'	FP Status register
    'B'  Cop0 register
    'C'  Cop2 register
@@ -3312,7 +3299,8 @@ typedef struct mips_args {
   {"consttable_operand",	{ LABEL_REF, SYMBOL_REF, CONST_INT,	\
 				  CONST_DOUBLE, CONST }},		\
   {"fcc_register_operand",	{ REG, SUBREG }},			\
-  {"hilo_operand",		{ REG }},
+  {"hilo_operand",		{ REG }},				\
+  {"extend_operator",		{ ZERO_EXTEND, SIGN_EXTEND }},
 
 /* A list of predicates that do special things with modes, and so
    should not elicit warnings for VOIDmode match_operand.  */
@@ -3546,7 +3534,7 @@ typedef struct mips_args {
   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",	\
   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",	\
   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",	\
-  "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",	\
+  "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",	\
   "$fcc5","$fcc6","$fcc7","$rap", "",     "",     "",     "",		\
   "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
   "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\