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Commit d2d604d8 by Jakub Jelinek Committed by Jakub Jelinek
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re PR target/90991 (_mm_loadu_ps instrinsic translates to vmovaps in combination… 

re PR target/90991 (_mm_loadu_ps instrinsic translates to vmovaps in combination with _mm512_insertf32x4)

	PR target/90991
	* config/i386/sse.md (avx_vec_concat<mode>): Use nonimmediate_operand
	instead of register_operand for operands[1], add m to its constraints
	if operands[2] uses "C" constraint.  Ensure in condition that if
	operands[2] is not 0, then operands[1] is not a MEM.  For last two
	alternatives, use unaligned loads instead of aligned if operands[1] is
	misaligned_operand.

	* gcc.target/i386/avx2-pr90991-1.c: New test.
	* gcc.target/i386/avx512dq-pr90991-2.c: New test.

From-SVN: r272745
parent 45309d28
Showing with 167 additions and 16 deletions
gcc/ChangeLog
2019-06-27 Jakub Jelinek <jakub@redhat.com>
PR target/90991
* config/i386/sse.md (avx_vec_concat<mode>): Use nonimmediate_operand
instead of register_operand for operands[1], add m to its constraints
if operands[2] uses "C" constraint. Ensure in condition that if
operands[2] is not 0, then operands[1] is not a MEM. For last two
alternatives, use unaligned loads instead of aligned if operands[1] is
misaligned_operand.
2019-06-27 Martin Liska <mliska@suse.cz>
* asan.c (asan_emit_allocas_unpoison): Remove obviously
......
gcc/config/i386/sse.md
......@@ -20743,9 +20743,11 @@
(define_insn "avx_vec_concat<mode>"
[(set (match_operand:V_256_512 0 "register_operand" "=x,v,x,Yv")
(vec_concat:V_256_512
(match_operand:<ssehalfvecmode> 1 "register_operand" "x,v,x,v")
(match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "x,v,xm,vm")
(match_operand:<ssehalfvecmode> 2 "nonimm_or_0_operand" "xm,vm,C,C")))]
"TARGET_AVX"
"TARGET_AVX
&& (operands[2] == CONST0_RTX (<ssehalfvecmode>mode)
|| !MEM_P (operands[1]))"
{
switch (which_alternative)
{
......@@ -20771,27 +20773,63 @@
switch (get_attr_mode (insn))
{
case MODE_V16SF:
return "vmovaps\t{%1, %t0|%t0, %1}";
if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
return "vmovups\t{%1, %t0|%t0, %1}";
else
return "vmovaps\t{%1, %t0|%t0, %1}";
case MODE_V8DF:
return "vmovapd\t{%1, %t0|%t0, %1}";
if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
return "vmovupd\t{%1, %t0|%t0, %1}";
else
return "vmovapd\t{%1, %t0|%t0, %1}";
case MODE_V8SF:
return "vmovaps\t{%1, %x0|%x0, %1}";
if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
return "vmovups\t{%1, %x0|%x0, %1}";
else
return "vmovaps\t{%1, %x0|%x0, %1}";
case MODE_V4DF:
return "vmovapd\t{%1, %x0|%x0, %1}";
if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
return "vmovupd\t{%1, %x0|%x0, %1}";
else
return "vmovapd\t{%1, %x0|%x0, %1}";
case MODE_XI:
if (which_alternative == 2)
return "vmovdqa\t{%1, %t0|%t0, %1}";
else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
return "vmovdqa64\t{%1, %t0|%t0, %1}";
if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
{
if (which_alternative == 2)
return "vmovdqu\t{%1, %t0|%t0, %1}";
else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
return "vmovdqu64\t{%1, %t0|%t0, %1}";
else
return "vmovdqu32\t{%1, %t0|%t0, %1}";
}
else
return "vmovdqa32\t{%1, %t0|%t0, %1}";
{
if (which_alternative == 2)
return "vmovdqa\t{%1, %t0|%t0, %1}";
else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
return "vmovdqa64\t{%1, %t0|%t0, %1}";
else
return "vmovdqa32\t{%1, %t0|%t0, %1}";
}
case MODE_OI:
if (which_alternative == 2)
return "vmovdqa\t{%1, %x0|%x0, %1}";
else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
return "vmovdqa64\t{%1, %x0|%x0, %1}";
if (misaligned_operand (operands[1], <ssehalfvecmode>mode))
{
if (which_alternative == 2)
return "vmovdqu\t{%1, %x0|%x0, %1}";
else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
return "vmovdqu64\t{%1, %x0|%x0, %1}";
else
return "vmovdqu32\t{%1, %x0|%x0, %1}";
}
else
return "vmovdqa32\t{%1, %x0|%x0, %1}";
{
if (which_alternative == 2)
return "vmovdqa\t{%1, %x0|%x0, %1}";
else if (GET_MODE_SIZE (<ssescalarmode>mode) == 8)
return "vmovdqa64\t{%1, %x0|%x0, %1}";
else
return "vmovdqa32\t{%1, %x0|%x0, %1}";
}
default:
gcc_unreachable ();
}
......
gcc/testsuite/ChangeLog
2019-06-27 Jakub Jelinek <jakub@redhat.com>
PR target/90991
* gcc.target/i386/avx2-pr90991-1.c: New test.
* gcc.target/i386/avx512dq-pr90991-2.c: New test.
2019-06-27 Jan Beulich <jbeulich@suse.com>
* gcc.target/i386/gfni-4.c: Pass -msse2.
......
gcc/testsuite/gcc.target/i386/avx2-pr90991-1.c 0 → 100644
/* PR target/90991 */
/* { dg-do compile } */
/* { dg-options "-O2 -mavx2 -masm=att" } */
/* { dg-final { scan-assembler-times "vmovaps\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovapd\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovdqa\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovups\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovupd\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovdqu\[ \t]\+\\(\[^\n\r]*\\), %xmm0" 1 } } */
/* { dg-final { scan-assembler-not "vmovaps\[^\n\r]*xmm0\[^\n\r]*xmm0" } } */
/* { dg-final { scan-assembler-not "vmovapd\[^\n\r]*xmm0\[^\n\r]*xmm0" } } */
/* { dg-final { scan-assembler-not "vmovdqa\[^\n\r]*xmm0\[^\n\r]*xmm0" } } */
#include <x86intrin.h>
__m256
f1 (void *a)
{
return _mm256_insertf128_ps (_mm256_set1_ps (0.0f), _mm_load_ps (a), 0);
}
__m256d
f2 (void *a)
{
return _mm256_insertf128_pd (_mm256_set1_pd (0.0), _mm_load_pd (a), 0);
}
__m256i
f3 (void *a)
{
return _mm256_insertf128_si256 (_mm256_set1_epi32 (0), _mm_load_si128 (a), 0);
}
__m256
f4 (void *a)
{
return _mm256_insertf128_ps (_mm256_set1_ps (0.0f), _mm_loadu_ps (a), 0);
}
__m256d
f5 (void *a)
{
return _mm256_insertf128_pd (_mm256_set1_pd (0.0), _mm_loadu_pd (a), 0);
}
__m256i
f6 (void *a)
{
return _mm256_insertf128_si256 (_mm256_set1_epi32 (0), _mm_loadu_si128 (a), 0);
}
gcc/testsuite/gcc.target/i386/avx512dq-pr90991-2.c 0 → 100644
/* PR target/90991 */
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512dq -masm=att -mtune=intel" } */
/* { dg-final { scan-assembler-times "vmovaps\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovapd\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovdqa\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovups\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovupd\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */
/* { dg-final { scan-assembler-times "vmovdqu\[ \t]\+\\(\[^\n\r]*\\), %ymm0" 1 } } */
#include <x86intrin.h>
__m512
f1 (void *a)
{
return _mm512_insertf32x8 (_mm512_set1_ps (0.0f), _mm256_load_ps (a), 0);
}
__m512d
f2 (void *a)
{
return _mm512_insertf64x4 (_mm512_set1_pd (0.0), _mm256_load_pd (a), 0);
}
__m512i
f3 (void *a)
{
return _mm512_inserti32x8 (_mm512_set1_epi32 (0), _mm256_load_si256 (a), 0);
}
__m512
f4 (void *a)
{
return _mm512_insertf32x8 (_mm512_set1_ps (0.0f), _mm256_loadu_ps (a), 0);
}
__m512d
f5 (void *a)
{
return _mm512_insertf64x4 (_mm512_set1_pd (0.0), _mm256_loadu_pd (a), 0);
}
__m512i
f6 (void *a)
{
return _mm512_inserti32x8 (_mm512_set1_epi32 (0), _mm256_loadu_si256 (a), 0);
}
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