Commit d2ceebd1 by Richard Earnshaw Committed by Richard Earnshaw

arm.md (*zeroextractqi_compare0_scratch): Re-add load instruction killed in previous change.

* config/arm/arm.md (*zeroextractqi_compare0_scratch): Re-add load
instruction killed in previous change.  Simplify mask generation.
(*zeroextractsi_compare0_scratch): Simpify mask generation.

From-SVN: r25241
parent e84aaeeb
Tue Feb 16 10:53:51 1999 Richard Earnshaw (rearnsha@arm.com)
* config/arm/arm.md (*zeroextractqi_compare0_scratch): Re-add load
instruction killed in previous change. Simplify mask generation.
(*zeroextractsi_compare0_scratch): Simpify mask generation.
Tue Feb 16 09:52:26 1999 Nick Clifton <nickc@cygnus.com> Tue Feb 16 09:52:26 1999 Nick Clifton <nickc@cygnus.com>
* config/arm/arm.md (zeroextractqi_compare0_scratch): Ensure that * config/arm/arm.md (zeroextractqi_compare0_scratch): Ensure that
......
...@@ -1193,16 +1193,10 @@ ...@@ -1193,16 +1193,10 @@
&& INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8 && INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 32" && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32"
"* "*
{ operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1)
unsigned int mask = 0; << INTVAL (operands[2]));
int cnt = INTVAL (operands[1]);
while (cnt--)
mask = (mask << 1) | 1;
operands[1] = GEN_INT (mask << INTVAL (operands[2]));
output_asm_insn (\"tst%?\\t%0, %1\", operands); output_asm_insn (\"tst%?\\t%0, %1\", operands);
return \"\"; return \"\";
}
" "
[(set_attr "conds" "set")]) [(set_attr "conds" "set")])
...@@ -1214,19 +1208,14 @@ ...@@ -1214,19 +1208,14 @@
(match_operand 2 "const_int_operand" "n")) (match_operand 2 "const_int_operand" "n"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:QI 3 "=r"))] (clobber (match_scratch:QI 3 "=r"))]
"INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) > 0 && "INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) > 0
((INTVAL (operands[1]) + INTVAL (operands[2])) <= 8)" && (INTVAL (operands[2]) + INTVAL (operands[1]) <= 8)"
"* "*
{ operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1)
unsigned int mask = 0; << INTVAL (operands[2]));
int cnt = INTVAL (operands[1]); output_asm_insn (\"ldr%?b\\t%3, %0\", operands);
while (cnt--)
mask = (mask << 1) | 1;
operands[1] = GEN_INT (mask << INTVAL (operands[2]));
output_asm_insn (\"tst%?\\t%3, %1\", operands); output_asm_insn (\"tst%?\\t%3, %1\", operands);
return \"\"; return \"\";
}
" "
[(set_attr "conds" "set") [(set_attr "conds" "set")
(set_attr "length" "8")]) (set_attr "length" "8")])
......
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