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Commit d1f87653 by Kazu Hirata Committed by Kazu Hirata
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athlon.md: Fix comment typos. 

	* config/i386/athlon.md: Fix comment typos.
	* config/i386/crtdll.h: Likewise.
	* config/i386/djgpp.h: Likewise.
	* config/i386/i386-interix.h: Likewise.
	* config/i386/i386.c: Likewise.
	* config/i386/i386.h: Likewise.
	* config/i386/i386.md: Likewise.
	* config/i386/k6.md: Likewise.
	* config/i386/mingw32.h: Likewise.
	* config/i386/pentium.md: Likewise.
	* config/i386/sco5.h: Likewise.
	* config/i386/winnt.c: Likewise.
	* config/i386/xmmintrin.h: Likewise.

From-SVN: r60524
parent eab5474f
Showing with 73 additions and 57 deletions
gcc/ChangeLog
2002-12-26 Kazu Hirata <kazu@cs.umass.edu>
* config/i386/athlon.md: Fix comment typos.
* config/i386/crtdll.h: Likewise.
* config/i386/djgpp.h: Likewise.
* config/i386/i386-interix.h: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/i386.h: Likewise.
* config/i386/i386.md: Likewise.
* config/i386/k6.md: Likewise.
* config/i386/mingw32.h: Likewise.
* config/i386/pentium.md: Likewise.
* config/i386/sco5.h: Likewise.
* config/i386/winnt.c: Likewise.
* config/i386/xmmintrin.h: Likewise.
2002-12-26 Jose Renau <renau@cs.uiuc.edu>
* ssa-dce.c (EXECUTE_IF_UNNECESSARY): Verify INSN is an
......
gcc/config/i386/athlon.md
......@@ -53,7 +53,7 @@
;; is used (this is needed to allow troughput of 1.5 double decoded
;; instructions per cycle).
;;
;; In order to avoid dependnece between reservation of decoder
;; In order to avoid dependence between reservation of decoder
;; and other units, we model decoder as two stage fully pipelined unit
;; and only double decoded instruction may occupy unit in the first cycle.
;; With this scheme however two double instructions can be issued cycle0.
......@@ -74,7 +74,7 @@
| (nothing,(athlon-decode0 + athlon-decode1))
| (nothing,(athlon-decode1 + athlon-decode2)))")
;; Agu and ieu unit results in extremly large automatons and
;; Agu and ieu unit results in extremely large automatons and
;; in our approximation they are hardly filled in. Only ieu
;; unit can, as issue rate is 3 and agu unit is always used
;; first in the insn reservations. Skip the models.
......@@ -107,7 +107,7 @@
(define_reservation "athlon-faddmul" "(athlon-fadd | athlon-fmul)")
;; Jump instructions are executed in the branch unit compltetely transparent to us
;; Jump instructions are executed in the branch unit completely transparent to us
(define_insn_reservation "athlon_branch" 0
(and (eq_attr "cpu" "athlon,k8")
(eq_attr "type" "ibr"))
......@@ -474,7 +474,7 @@
(and (eq_attr "cpu" "athlon,k8")
(eq_attr "unit" "mmx"))
"athlon-direct,athlon-faddmul")
;; SSE operations are handled by the i387 unit as well. The latnecy
;; SSE operations are handled by the i387 unit as well. The latency
;; is same as for i387 operations for scalar operations
(define_insn_reservation "athlon_sselog_load" 6
(and (eq_attr "cpu" "athlon")
......
gcc/config/i386/crtdll.h
/* Operating system specific defines to be used when targeting GCC for
hosting on Windows32, using GNU tools and the Windows32 API Library.
This variant uses CRTDLL.DLL insted of MSVCRTDLL.DLL.
This variant uses CRTDLL.DLL instead of MSVCRTDLL.DLL.
Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.
This file is part of GNU CC.
......
gcc/config/i386/djgpp.h
......@@ -63,7 +63,7 @@ Boston, MA 02111-1307, USA. */
/* Define standard DJGPP installation paths. */
/* We override default /usr or /usr/local part with /dev/env/DJDIR which */
/* points to actual DJGPP instalation directory. */
/* points to actual DJGPP installation directory. */
/* Standard include directory */
#undef STANDARD_INCLUDE_DIR
......
gcc/config/i386/i386-interix.h
......@@ -36,7 +36,7 @@ Boston, MA 02111-1307, USA. */
/* By default, target has a 80387, uses IEEE compatible arithmetic,
and returns float values in the 387 and needs stack probes
We also align doubles to 64-bits for MSVC default compatibility
We do bitfields MSVC-compatably by default, too. */
We do bitfields MSVC-compatibly by default, too. */
#undef TARGET_SUBTARGET_DEFAULT
#define TARGET_SUBTARGET_DEFAULT \
(MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE | \
......
gcc/config/i386/i386.h
......@@ -745,12 +745,12 @@ extern int x86_prefetch_sse;
/* Boundary (in *bits*) on which stack pointer should be aligned. */
#define STACK_BOUNDARY BITS_PER_WORD
/* Boundary (in *bits*) on which the stack pointer preferrs to be
/* Boundary (in *bits*) on which the stack pointer prefers to be
aligned; the compiler cannot rely on having this alignment. */
#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
/* As of July 2001, many runtimes to not align the stack properly when
entering main. This causes expand_main_function to forcably align
entering main. This causes expand_main_function to forcibly align
the stack, which results in aligned frames for functions called from
main, though it does nothing for the alignment of main itself. */
#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
......@@ -771,7 +771,7 @@ extern int x86_prefetch_sse;
might need to be aligned. No data type wants to be aligned
rounder than this.
Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
Pentium+ prefers DFmode values to be aligned to 64 bit boundary
and Pentium Pro XFmode values at 128 bit boundaries. */
#define BIGGEST_ALIGNMENT 128
......@@ -781,7 +781,7 @@ extern int x86_prefetch_sse;
((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
/* The published ABIs say that doubles should be aligned on word
boundaries, so lower the aligment for structure fields unless
boundaries, so lower the alignment for structure fields unless
-malign-double is set. */
/* ??? Blah -- this macro is used directly by libobjc. Since it
......@@ -952,7 +952,7 @@ extern int x86_prefetch_sse;
/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
to be rearranged based on a particular function. When using sse math,
we want to allocase SSE before x87 registers and vice vera. */
we want to allocate SSE before x87 registers and vice vera. */
#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
......@@ -1441,7 +1441,7 @@ enum reg_class
K is for signed imm8 operands.
L is for andsi as zero-extending move.
M is for shifts that can be executed by the "lea" opcode.
N is for immedaite operands for out/in instructions (0-255)
N is for immediate operands for out/in instructions (0-255)
*/
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
......
gcc/config/i386/k6.md
......@@ -31,7 +31,7 @@
;; fpu describes FPU unit
;; load describes load unit.
;; branch describes branch unit.
;; store decsribes store unit. This unit is not modelled completely and only
;; store describes store unit. This unit is not modelled completely and only
;; used to model lea operation. Otherwise it lie outside of the critical
;; path.
;;
......
gcc/config/i386/mingw32.h
......@@ -32,7 +32,7 @@ Boston, MA 02111-1307, USA. */
#define TARGET_EXECUTABLE_SUFFIX ".exe"
/* See i386/crtdll.h for an altervative definition. */
/* See i386/crtdll.h for an alternative definition. */
#define EXTRA_OS_CPP_BUILTINS() \
do \
{ \
......@@ -102,7 +102,7 @@ Boston, MA 02111-1307, USA. */
#define MATH_LIBRARY ""
/* Output STRING, a string representing a filename, to FILE.
We canonicalize it to be in Unix format (backslashe are replaced
We canonicalize it to be in Unix format (backslashes are replaced
forward slashes. */
#undef OUTPUT_QUOTED_STRING
#define OUTPUT_QUOTED_STRING(FILE, STRING) \
......@@ -129,6 +129,6 @@ do { \
putc ('\"', asm_file); \
} while (0)
/* Define as short unsigned for compatability with MS runtime. */
/* Define as short unsigned for compatibility with MS runtime. */
#undef WINT_TYPE
#define WINT_TYPE "short unsigned int"
gcc/config/i386/pentium.md
......@@ -34,7 +34,7 @@
;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
;; rules, because it results in noticeably better code on non-MMX Pentium
;; and doesn't hurt much on MMX. (Prefixed instructions are not very
;; common, so the scheduler usualy has a non-prefixed insn to pair).
;; common, so the scheduler usually has a non-prefixed insn to pair).
(define_attr "pent_pair" "uv,pu,pv,np"
(cond [(eq_attr "imm_disp" "true")
......@@ -71,7 +71,7 @@
(define_automaton "pentium,pentium_fpu")
;; Pentium do have U and V pipes. Instruction to both pipes
;; are alwyas issued together, much like on VLIW.
;; are always issued together, much like on VLIW.
;;
;; predecode
;; / \
......
gcc/config/i386/sco5.h
......@@ -72,7 +72,7 @@ Boston, MA 02111-1307, USA. */
#define EH_FRAME_SECTION_NAME \
((TARGET_ELF) ? EH_FRAME_SECTION_NAME_ELF : EH_FRAME_SECTION_NAME_COFF)
/* Avoid problems (long sectino names, forward assembler refs) with DWARF
/* Avoid problems (long section names, forward assembler refs) with DWARF
exception unwinding when we're generating COFF */
#define DWARF2_UNWIND_INFO \
((TARGET_ELF) ? 1 : 0 )
......
gcc/config/i386/winnt.c
......@@ -579,7 +579,7 @@ i386_pe_unique_section (decl, reloc)
If the section has already been defined, to not allow it to have
different attributes, as (1) this is ambiguous since we're not seeing
all the declarations up front and (2) some assemblers (e.g. SVR4)
do not recoginize section redefinitions. */
do not recognize section redefinitions. */
/* ??? This differs from the "standard" PE implementation in that we
handle the SHARED variable attribute. Should this be done for all
PE targets? */
......
gcc/config/i386/xmmintrin.h
......@@ -37,10 +37,10 @@
/* We need type definitions from the MMX header file. */
#include <mmintrin.h>
/* The data type indended for user use. */
/* The data type intended for user use. */
typedef int __m128 __attribute__ ((__mode__(__V4SF__)));
/* Internal data types for implementing the instrinsics. */
/* Internal data types for implementing the intrinsics. */
typedef int __v4sf __attribute__ ((__mode__(__V4SF__)));
typedef int __v4si __attribute__ ((__mode__(__V4SI__)));
......@@ -1047,7 +1047,7 @@ _mm_stream_ps (float *__P, __m128 __A)
__builtin_ia32_movntps (__P, (__v4sf)__A);
}
/* Guarantees that every preceeding store is globally visible before
/* Guarantees that every preceding store is globally visible before
any subsequent store. */
static __inline void
_mm_sfence (void)
......@@ -1114,21 +1114,21 @@ _mm_load_pd1 (double const *__P)
return _mm_load1_pd (__P);
}
/* Load two DPFP values from P. The addresd must be 16-byte aligned. */
/* Load two DPFP values from P. The address must be 16-byte aligned. */
static __inline __m128d
_mm_load_pd (double const *__P)
{
return (__m128d) __builtin_ia32_loadapd (__P);
}
/* Load two DPFP values from P. The addresd need not be 16-byte aligned. */
/* Load two DPFP values from P. The address need not be 16-byte aligned. */
static __inline __m128d
_mm_loadu_pd (double const *__P)
{
return (__m128d) __builtin_ia32_loadupd (__P);
}
/* Load two DPFP values in reverse order. The addresd must be aligned. */
/* Load two DPFP values in reverse order. The address must be aligned. */
static __inline __m128d
_mm_loadr_pd (double const *__P)
{
......@@ -1208,21 +1208,21 @@ _mm_store_pd1 (double *__P, __m128d __A)
_mm_store1_pd (__P, __A);
}
/* Store two DPFP values. The addresd must be 16-byte aligned. */
/* Store two DPFP values. The address must be 16-byte aligned. */
static __inline void
_mm_store_pd (double *__P, __m128d __A)
{
__builtin_ia32_storeapd (__P, (__v2df)__A);
}
/* Store two DPFP values. The addresd need not be 16-byte aligned. */
/* Store two DPFP values. The address need not be 16-byte aligned. */
static __inline void
_mm_storeu_pd (double *__P, __m128d __A)
{
__builtin_ia32_storeupd (__P, (__v2df)__A);
}
/* Store two DPFP values in reverse order. The addresd must be aligned. */
/* Store two DPFP values in reverse order. The address must be aligned. */
static __inline void
_mm_storer_pd (double *__P, __m128d __A)
{
......
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