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riscv-gcc-1
Commit d1c3b587 by H.J. Lu
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i386.md (sat_plusminus): New. 

2008-05-05  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.md (sat_plusminus): New.
	(plusminus_insn): Likewise.
	(plusminus_mnemonic): Likewise.
	(addsub): Removed.
	(comm): Add ss_plus, us_plus, ss_minus and us_minus.
	(*<addsub><mode>3_cc_overflow): Renamed to ...
	(*<plusminus_insn><mode>3_cc_overflow): This.
	(*<addsub>si3_zext_cc_overflow): Renamed to ...
	(*<plusminus_insn>si3_zext_cc_overflow): This.

	* gcc/config/i386/sse.md (<addsub><mode>3): Renamed to ...
	(<plusminus_insn><mode>3): This.
	(*<addsub><mode>3): Renamed to ...
	(*<plusminus_insn><mode>3): This.
	(<sse>_vm<addsub><mode>3): Renamed to ...
	(<sse>_vm<plusminus_insn><mode>3): This.
	(sse3_h<addsub>v4sf3): Renamed to ...
	(sse3_h<plusminus_insn>v4sf3): This.
	(sse3_h<addsub>v2df3): Renamed to ...
	(sse3_h<plusminus_insn>v2df3): This.
	(<plusminus_insn><mode>3): New.
	(*<plusminus_insn><mode>3): Likewise.
	(sse2_<plusminus_insn><mode>3): Likewise.
	(add<mode>): Removed.
	(*add<mode>3): Likewise.
	(sse2_ssadd<mode>3): Likewise.
	(sse2_usadd<mode>3): Likewise.
	(sub<mode>3): Likewise.
	(*sub<mode>3): Likewise.
	(sse2_sssub<mode>3): Likewise.
	(sse2_ussub<mode>3): Likewise.

From-SVN: r134957
parent 33437ca0
Showing with 84 additions and 90 deletions
gcc/ChangeLog
2008-05-05 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.md (sat_plusminus): New.
(plusminus_insn): Likewise.
(plusminus_mnemonic): Likewise.
(addsub): Removed.
(comm): Add ss_plus, us_plus, ss_minus and us_minus.
(*<addsub><mode>3_cc_overflow): Renamed to ...
(*<plusminus_insn><mode>3_cc_overflow): This.
(*<addsub>si3_zext_cc_overflow): Renamed to ...
(*<plusminus_insn>si3_zext_cc_overflow): This.
* gcc/config/i386/sse.md (<addsub><mode>3): Renamed to ...
(<plusminus_insn><mode>3): This.
(*<addsub><mode>3): Renamed to ...
(*<plusminus_insn><mode>3): This.
(<sse>_vm<addsub><mode>3): Renamed to ...
(<sse>_vm<plusminus_insn><mode>3): This.
(sse3_h<addsub>v4sf3): Renamed to ...
(sse3_h<plusminus_insn>v4sf3): This.
(sse3_h<addsub>v2df3): Renamed to ...
(sse3_h<plusminus_insn>v2df3): This.
(<plusminus_insn><mode>3): New.
(*<plusminus_insn><mode>3): Likewise.
(sse2_<plusminus_insn><mode>3): Likewise.
(add<mode>): Removed.
(*add<mode>3): Likewise.
(sse2_ssadd<mode>3): Likewise.
(sse2_usadd<mode>3): Likewise.
(sub<mode>3): Likewise.
(*sub<mode>3): Likewise.
(sse2_sssub<mode>3): Likewise.
(sse2_ussub<mode>3): Likewise.
2008-05-05 Benjamin Kosnik <bkoz@redhat.com>
* gthr-single.h: Add in required interface elements as per gthr.h.
Add stub types for __gthread_key_t, __gthread_once_t. Add defines
for __GTHREAD_ONCE_INIT, __GTHREAD_RECURSIVE_MUTEX_INIT.
Generalize UNUSED macro.
(__gthread_once): Add.
(__gthread_key_create): Add.
(__gthread_key_delete): Add.
(__gthread_getspecific): Add.
(__gthread_setspecific): Add.
* gthr-single.h: Add in required interface elements as per gthr.h.
Add stub types for __gthread_key_t, __gthread_once_t. Add defines
for __GTHREAD_ONCE_INIT, __GTHREAD_RECURSIVE_MUTEX_INIT.
Generalize UNUSED macro.
(__gthread_once): Add.
(__gthread_key_create): Add.
(__gthread_key_delete): Add.
(__gthread_getspecific): Add.
(__gthread_setspecific): Add.
2008-05-05 Andrew Pinski <Andrew.Pinski@playstation.sony.com>
......
gcc/config/i386/i386.md
......@@ -535,11 +535,21 @@
(define_code_iterator plusminus [plus minus])
;; Base name for define_insn and insn mnemonic.
(define_code_attr addsub [(plus "add") (minus "sub")])
(define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus])
;; Base name for define_insn
(define_code_attr plusminus_insn
[(plus "add") (ss_plus "ssadd") (us_plus "usadd")
(minus "sub") (ss_minus "sssub") (us_minus "ussub")])
;; Base name for insn mnemonic.
(define_code_attr plusminus_mnemonic
[(plus "add") (ss_plus "adds") (us_plus "addus")
(minus "sub") (ss_minus "subs") (us_minus "subus")])
;; Mark commutative operators as such in constraints.
(define_code_attr comm [(plus "%") (minus "")])
(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")
(minus "") (ss_minus "") (us_minus "")])
;; Mapping of signed max and min
(define_code_iterator smaxmin [smax smin])
......@@ -5582,7 +5592,7 @@
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(define_insn "*<addsub><mode>3_cc_overflow"
(define_insn "*<plusminus_insn><mode>3_cc_overflow"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(plusminus:SWI
......@@ -5592,7 +5602,7 @@
(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
(plusminus:SWI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<addsub>{<imodesuffix>}\t{%2, %0|%0, %2}"
"<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
......@@ -5619,7 +5629,7 @@
[(set_attr "type" "icmp")
(set_attr "mode" "<MODE>")])
(define_insn "*<addsub>si3_zext_cc_overflow"
(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(plusminus:SI (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
......@@ -5628,7 +5638,7 @@
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
"<addsub>{l}\t{%2, %k0|%k0, %2}"
"<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
......
gcc/config/i386/sse.md
......@@ -302,7 +302,7 @@
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
(define_expand "<addsub><mode>3"
(define_expand "<plusminus_insn><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
(plusminus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
......@@ -310,18 +310,18 @@
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<addsub><mode>3"
(define_insn "*<plusminus_insn><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(plusminus:SSEMODEF2P
(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "<comm>0")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<addsub>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
"<plusminus_mnemonic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
(define_insn "<sse>_vm<addsub><mode>3"
(define_insn "<sse>_vm<plusminus_insn><mode>3"
[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
(vec_merge:SSEMODEF2P
(plusminus:SSEMODEF2P
......@@ -331,7 +331,7 @@
(const_int 1)))]
"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
&& ix86_binary_operator_ok (<CODE>, V4SFmode, operands)"
"<addsub>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
"<plusminus_mnemonic>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<ssescalarmode>")])
......@@ -615,7 +615,7 @@
[(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")])
(define_insn "sse3_h<addsub>v4sf3"
(define_insn "sse3_h<plusminus_insn>v4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_concat:V4SF
(vec_concat:V2SF
......@@ -637,12 +637,12 @@
(vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
(vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
"TARGET_SSE3"
"h<addsub>ps\t{%2, %0|%0, %2}"
"h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")])
(define_insn "sse3_h<addsub>v2df3"
(define_insn "sse3_h<plusminus_insn>v2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_concat:V2DF
(plusminus:DF
......@@ -656,7 +656,7 @@
(parallel [(const_int 0)]))
(vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
"TARGET_SSE3"
"h<addsub>pd\t{%2, %0|%0, %2}"
"h<plusminus_mnemonic>pd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "V2DF")])
......@@ -2722,82 +2722,32 @@
"TARGET_SSE2"
"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
(define_expand "add<mode>3"
(define_expand "<plusminus_insn><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "")
(plus:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);")
(define_insn "*add<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(plus:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
"padd<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ssadd<mode>3"
[(set (match_operand:SSEMODE12 0 "register_operand" "=x")
(ss_plus:SSEMODE12
(match_operand:SSEMODE12 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (SS_PLUS, <MODE>mode, operands)"
"padds<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_usadd<mode>3"
[(set (match_operand:SSEMODE12 0 "register_operand" "=x")
(us_plus:SSEMODE12
(match_operand:SSEMODE12 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (US_PLUS, <MODE>mode, operands)"
"paddus<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "sub<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "")
(minus:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
(plusminus:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands);")
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*sub<mode>3"
(define_insn "*<plusminus_insn><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(minus:SSEMODEI
(match_operand:SSEMODEI 1 "register_operand" "0")
(plusminus:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psub<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_sssub<mode>3"
[(set (match_operand:SSEMODE12 0 "register_operand" "=x")
(ss_minus:SSEMODE12
(match_operand:SSEMODE12 1 "register_operand" "0")
(match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubs<ssevecsize>\t{%2, %0|%0, %2}"
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ussub<mode>3"
(define_insn "sse2_<plusminus_insn><mode>3"
[(set (match_operand:SSEMODE12 0 "register_operand" "=x")
(us_minus:SSEMODE12
(match_operand:SSEMODE12 1 "register_operand" "0")
(sat_plusminus:SSEMODE12
(match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>0")
(match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubus<ssevecsize>\t{%2, %0|%0, %2}"
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"p<sat_plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
......
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