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riscv-gcc-1
Commit d1ab0a32 by Claudiu Zissulescu Committed by Claudiu Zissulescu
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[ARC] Update ARC SIMD patterns. 

vec_select expects in selection a list of subparts. The old ARC SIMD
extension instructions were not up-to-date.

gcc/
2017-03-28  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/simdext.md (vst64_insn): Update pattern.
	(vld32wh_insn): Likewise.
	(vld32wl_insn): Likewise.
	(vld64_insn): Likewise.
	(vld32_insn): Likewise.

From-SVN: r246523
parent 72785f26
Showing with 75 additions and 31 deletions
gcc/ChangeLog
2017-03-28 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/simdext.md (vst64_insn): Update pattern.
(vld32wh_insn): Likewise.
(vld32wl_insn): Likewise.
(vld64_insn): Likewise.
(vld32_insn): Likewise.
2017-03-28 Marek Polacek <polacek@redhat.com> 2017-03-28 Marek Polacek <polacek@redhat.com>
PR sanitizer/80067 PR sanitizer/80067
......
gcc/config/arc/simdext.md
...@@ -193,11 +193,16 @@ ...@@ -193,11 +193,16 @@
) )
(define_insn "vst64_insn" (define_insn "vst64_insn"
[(set (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v") [(set (mem:V4HI
(parallel [(match_operand:SI 1 "immediate_operand" "L")]))) (plus:SI
(match_operand:SI 2 "immediate_operand" "P"))) (zero_extend:SI
(vec_select:V4HI (match_operand:V8HI 3 "vector_register_operand" "=v") (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v")
(parallel [(const_int 0)])))] (parallel
[(match_operand:SI 1 "immediate_operand" "L")])))
(match_operand:SI 2 "immediate_operand" "P")))
(vec_select:V4HI
(match_operand:V8HI 3 "vector_register_operand" "=v")
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))]
"TARGET_SIMD_SET" "TARGET_SIMD_SET"
"vst64 %3, [i%1, %2]" "vst64 %3, [i%1, %2]"
[(set_attr "type" "simd_vstore") [(set_attr "type" "simd_vstore")
...@@ -1191,12 +1196,20 @@ ...@@ -1191,12 +1196,20 @@
(set_attr "cond" "nocond")]) (set_attr "cond" "nocond")])
(define_insn "vld32wh_insn" (define_insn "vld32wh_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v") [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(vec_concat:V8HI (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P") (vec_concat:V8HI
(zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v") (zero_extend:V4HI
(parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) (mem:V4QI
(vec_select:V4HI (match_dup 0) (plus:SI
(parallel [(const_int 0)]))))] (match_operand:SI 1 "immediate_operand" "P")
(zero_extend:SI
(vec_select:HI
(match_operand:V8HI 2 "vector_register_operand" "v")
(parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))
(vec_select:V4HI
(match_dup 0)
(parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])
)))]
"TARGET_SIMD_SET" "TARGET_SIMD_SET"
"vld32wh %0, [i%3,%1]" "vld32wh %0, [i%3,%1]"
[(set_attr "type" "simd_vload") [(set_attr "type" "simd_vload")
...@@ -1204,12 +1217,20 @@ ...@@ -1204,12 +1217,20 @@
(set_attr "cond" "nocond")]) (set_attr "cond" "nocond")])
(define_insn "vld32wl_insn" (define_insn "vld32wl_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v") [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(vec_concat:V8HI (vec_select:V4HI (match_dup 0) (vec_concat:V8HI
(parallel [(const_int 1)])) (vec_select:V4HI
(zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P") (match_dup 0)
(zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
(parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))] (zero_extend:V4HI
(mem:V4QI
(plus:SI
(match_operand:SI 1 "immediate_operand" "P")
(zero_extend:SI
(vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
(parallel
[(match_operand:SI 3 "immediate_operand" "L")]))
))))))]
"TARGET_SIMD_SET" "TARGET_SIMD_SET"
"vld32wl %0, [i%3,%1]" "vld32wl %0, [i%3,%1]"
[(set_attr "type" "simd_vload") [(set_attr "type" "simd_vload")
...@@ -1229,12 +1250,19 @@ ...@@ -1229,12 +1250,19 @@
) )
(define_insn "vld64_insn" (define_insn "vld64_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v") [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(vec_concat:V8HI (vec_select:V4HI (match_dup 0) (vec_concat:V8HI
(parallel [(const_int 1)])) (vec_select:V4HI
(mem:V4HI (plus:SI (match_operand:SI 1 "immediate_operand" "P") (match_dup 0)
(zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
(parallel [(match_operand:SI 3 "immediate_operand" "L")]))))) ))] (mem:V4HI
(plus:SI
(match_operand:SI 1 "immediate_operand" "P")
(zero_extend:SI
(vec_select:HI
(match_operand:V8HI 2 "vector_register_operand" "v")
(parallel [(match_operand:SI 3 "immediate_operand" "L")]))
)))))]
"TARGET_SIMD_SET" "TARGET_SIMD_SET"
"vld64 %0, [i%3,%1]" "vld64 %0, [i%3,%1]"
[(set_attr "type" "simd_vload") [(set_attr "type" "simd_vload")
...@@ -1242,14 +1270,22 @@ ...@@ -1242,14 +1270,22 @@
(set_attr "cond" "nocond")]) (set_attr "cond" "nocond")])
(define_insn "vld32_insn" (define_insn "vld32_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v") [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(vec_concat:V8HI (vec_select:V4HI (match_dup 0) (vec_concat:V8HI
(parallel [(const_int 1)])) (vec_select:V4HI
(vec_concat:V4HI (vec_select:V2HI (match_dup 0) (match_dup 0)
(parallel [(const_int 1)])) (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
(mem:V2HI (plus:SI (match_operand:SI 1 "immediate_operand" "P") (vec_concat:V4HI
(zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v") (vec_select:V2HI
(parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))] (match_dup 0)
(parallel [(const_int 2) (const_int 3)]))
(mem:V2HI
(plus:SI
(match_operand:SI 1 "immediate_operand" "P")
(zero_extend:SI
(vec_select:HI
(match_operand:V8HI 2 "vector_register_operand" "v")
(parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))))]
"TARGET_SIMD_SET" "TARGET_SIMD_SET"
"vld32 %0, [i%3,%1]" "vld32 %0, [i%3,%1]"
[(set_attr "type" "simd_vload") [(set_attr "type" "simd_vload")
......
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