Commit d0e2a1f8 by Eric Botcazou Committed by Eric Botcazou

re PR target/49965 (libgomp.c++/reduction-4.C and libgomp.c++/task-8.C FAIL on Solaris 11/SPARC)

	PR target/49965
	* config/sparc/sparc.md (mov<I:mode>cc): Do not save comparison code.
	(mov<F:mode>cc): Likewise.

From-SVN: r179827
parent 60ca0fe6
2011-10-11 Eric Botcazou <ebotcazou@adacore.com>
PR target/49965
* config/sparc/sparc.md (mov<I:mode>cc): Do not save comparison code.
(mov<F:mode>cc): Likewise.
2011-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com> 2011-10-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* tree-ssa-address.c (copy_ref_info): Remove copy of TREE_THIS_NOTRAP. * tree-ssa-address.c (copy_ref_info): Remove copy of TREE_THIS_NOTRAP.
...@@ -2614,11 +2614,9 @@ ...@@ -2614,11 +2614,9 @@
(match_operand:I 3 "arith10_operand" "")))] (match_operand:I 3 "arith10_operand" "")))]
"TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)" "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
{ {
enum rtx_code code = GET_CODE (operands[1]);
rtx cc_reg; rtx cc_reg;
if (GET_MODE (XEXP (operands[1], 0)) == DImode if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
&& ! TARGET_ARCH64)
FAIL; FAIL;
if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD) if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
...@@ -2629,12 +2627,14 @@ ...@@ -2629,12 +2627,14 @@
if (XEXP (operands[1], 1) == const0_rtx if (XEXP (operands[1], 1) == const0_rtx
&& GET_CODE (XEXP (operands[1], 0)) == REG && GET_CODE (XEXP (operands[1], 0)) == REG
&& GET_MODE (XEXP (operands[1], 0)) == DImode && GET_MODE (XEXP (operands[1], 0)) == DImode
&& v9_regcmp_p (code)) && v9_regcmp_p (GET_CODE (operands[1])))
cc_reg = XEXP (operands[1], 0); cc_reg = XEXP (operands[1], 0);
else else
cc_reg = gen_compare_reg (operands[1]); cc_reg = gen_compare_reg (operands[1]);
operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); operands[1]
= gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
const0_rtx);
}) })
(define_expand "mov<F:mode>cc" (define_expand "mov<F:mode>cc"
...@@ -2644,11 +2644,9 @@ ...@@ -2644,11 +2644,9 @@
(match_operand:F 3 "register_operand" "")))] (match_operand:F 3 "register_operand" "")))]
"TARGET_V9 && TARGET_FPU" "TARGET_V9 && TARGET_FPU"
{ {
enum rtx_code code = GET_CODE (operands[1]);
rtx cc_reg; rtx cc_reg;
if (GET_MODE (XEXP (operands[1], 0)) == DImode if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
&& ! TARGET_ARCH64)
FAIL; FAIL;
if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD) if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
...@@ -2659,12 +2657,14 @@ ...@@ -2659,12 +2657,14 @@
if (XEXP (operands[1], 1) == const0_rtx if (XEXP (operands[1], 1) == const0_rtx
&& GET_CODE (XEXP (operands[1], 0)) == REG && GET_CODE (XEXP (operands[1], 0)) == REG
&& GET_MODE (XEXP (operands[1], 0)) == DImode && GET_MODE (XEXP (operands[1], 0)) == DImode
&& v9_regcmp_p (code)) && v9_regcmp_p (GET_CODE (operands[1])))
cc_reg = XEXP (operands[1], 0); cc_reg = XEXP (operands[1], 0);
else else
cc_reg = gen_compare_reg (operands[1]); cc_reg = gen_compare_reg (operands[1]);
operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); operands[1]
= gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
const0_rtx);
}) })
;; Conditional move define_insns ;; Conditional move define_insns
......
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