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lvzhengyang
riscv-gcc-1
Commits
d0b6bb1b
Commit
d0b6bb1b
authored
Jan 16, 2013
by
Ian Bolton
Committed by
Ian Bolton
Jan 16, 2013
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Make zero_extends explicit for some more SImode patterns (AArch64)
From-SVN: r195243
parent
f34dea03
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gcc/config/aarch64/aarch64.md
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gcc/ChangeLog
View file @
d0b6bb1b
2013-01-16 Ian Bolton <ian.bolton@arm.com>
* gcc/config/aarch64/aarch64.md
(*cstoresi_neg_uxtw): New pattern.
(*cmovsi_insn_uxtw): New pattern.
(*<optab>si3_uxtw): New pattern.
(*<LOGICAL:optab>_<SHIFT:optab>si3_uxtw): New pattern.
(*<optab>si3_insn_uxtw): New pattern.
(*bswapsi2_uxtw): New pattern.
2013-01-16 Richard Biener <rguenther@suse.de>
* tree-inline.c (tree_function_versioning): Remove set but
...
...
gcc/config/aarch64/aarch64.md
View file @
d0b6bb1b
...
...
@@ -2198,6 +2198,18 @@
(set_attr "mode" "
<MODE>
")]
)
;; zero_extend version of the above
(define_insn "
*
cstoresi_insn_uxtw"
[
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(match_operator:SI 1 "aarch64_comparison_operator"
[
(match_operand 2 "cc_register" "") (const_int 0)
]
)))]
""
"cset
\\
t%w0, %m1"
[
(set_attr "v8type" "csel")
(set_attr "mode" "SI")]
)
(define_insn "
*
cstore
<mode>
_neg"
[
(set (match_operand:ALLI 0 "register_operand" "=r")
(neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator"
...
...
@@ -2208,6 +2220,18 @@
(set_attr "mode" "
<MODE>
")]
)
;; zero_extend version of the above
(define_insn "
*
cstoresi_neg_uxtw"
[
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(neg:SI (match_operator:SI 1 "aarch64_comparison_operator"
[
(match_operand 2 "cc_register" "") (const_int 0)
]
))))]
""
"csetm
\\
t%w0, %m1"
[
(set_attr "v8type" "csel")
(set_attr "mode" "SI")]
)
(define_expand "cmov
<mode>
6"
[
(set (match_operand:GPI 0 "register_operand" "")
(if_then_else:GPI
...
...
@@ -2262,6 +2286,30 @@
(set_attr "mode" "
<MODE>
")]
)
;; zero_extend version of above
(define_insn "
*
cmovsi_insn_uxtw"
[
(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r")
(zero_extend:DI
(if_then_else:SI
(match_operator 1 "aarch64_comparison_operator"
[
(match_operand 2 "cc_register" "") (const_int 0)
]
)
(match_operand:SI 3 "aarch64_reg_zero_or_m1_or_1" "rZ,rZ,UsM,rZ,Ui1,UsM,Ui1")
(match_operand:SI 4 "aarch64_reg_zero_or_m1_or_1" "rZ,UsM,rZ,Ui1,rZ,UsM,Ui1"))))]
"!((operands
[
3
]
== const1_rtx && operands
[
4
]
== constm1_rtx)
|| (operands
[
3
]
== constm1_rtx && operands
[
4
]
== const1_rtx))"
;; Final two alternatives should be unreachable, but included for completeness
"@
csel
\\
t%w0, %w3, %w4, %m1
csinv
\\
t%w0, %w3, wzr, %m1
csinv
\\
t%w0, %w4, wzr, %M1
csinc
\\
t%w0, %w3, wzr, %m1
csinc
\\
t%w0, %w4, wzr, %M1
mov
\\
t%w0, -1
mov
\\
t%w0, 1"
[
(set_attr "v8type" "csel")
(set_attr "mode" "SI")]
)
(define_insn "
*
cmov
<mode>
_insn"
[
(set (match_operand:GPF 0 "register_operand" "=w")
(if_then_else:GPF
...
...
@@ -2374,6 +2422,17 @@
[
(set_attr "v8type" "logic,logic_imm")
(set_attr "mode" "
<MODE>
")])
;; zero_extend version of above
(define_insn "
*
<optab>
si3_uxtw"
[
(set (match_operand:DI 0 "register_operand" "=r,rk")
(zero_extend:DI
(LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r")
(match_operand:SI 2 "aarch64_logical_operand" "r,K"))))]
""
"
<logical>
\\
t%w0, %w1, %w2"
[
(set_attr "v8type" "logic,logic_imm")
(set_attr "mode" "SI")])
(define_insn "
*
<LOGICAL:optab>
_
<SHIFT:optab><mode>
3"
[
(set (match_operand:GPI 0 "register_operand" "=r")
(LOGICAL:GPI (SHIFT:GPI
...
...
@@ -2385,6 +2444,19 @@
[
(set_attr "v8type" "logic_shift")
(set_attr "mode" "
<MODE>
")])
;; zero_extend version of above
(define_insn "
*
<LOGICAL:optab>
_<SHIFT:optab>si3_
uxtw"
[
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(LOGICAL:SI (SHIFT:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_si" "n"))
(match_operand:SI 3 "register_operand" "r"))))]
""
"
<LOGICAL:logical>
\\
t%w0, %w3, %w1,
<SHIFT:shift>
%2"
[
(set_attr "v8type" "logic_shift")
(set_attr "mode" "SI")])
(define_insn "one_cmpl
<mode>
2"
[
(set (match_operand:GPI 0 "register_operand" "=r")
(not:GPI (match_operand:GPI 1 "register_operand" "r")))]
...
...
@@ -2596,6 +2668,18 @@
(set_attr "mode" "
<MODE>
")]
)
;; zero_extend version of above
(define_insn "
*
<optab>
si3_insn_uxtw"
[
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (SHIFT:SI
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))]
""
"
<shift>
\\
t%w0, %w1, %w2"
[
(set_attr "v8type" "shift")
(set_attr "mode" "SI")]
)
(define_insn "
*
ashl
<mode>
3_insn"
[
(set (match_operand:SHORT 0 "register_operand" "=r")
(ashift:SHORT (match_operand:SHORT 1 "register_operand" "r")
...
...
@@ -2733,6 +2817,16 @@
(set_attr "mode" "HI")]
)
;; zero_extend version of above
(define_insn "
*
bswapsi2_uxtw"
[
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (bswap:SI (match_operand:SI 1 "register_operand" "r"))))]
""
"rev
\\
t%w0, %w1"
[
(set_attr "v8type" "rev")
(set_attr "mode" "SI")]
)
;; -------------------------------------------------------------------
;; Floating-point intrinsics
;; -------------------------------------------------------------------
...
...
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