rs6000.md: Add fixuns_truncsfsi2 and fix_truncsfsi2.

2004-02-26  Aldy Hernandez  <aldyh@redhat.com>

	* config/rs6000/rs6000.md: Add fixuns_truncsfsi2 and
	fix_truncsfsi2.

	* config/rs6000/spe.md: Delete spe_efsctuiz.
	Add spe_fixuns_truncsfsi2.
	Add spe_fix_truncsfsi2.

[[Split portion of a mixed commit.]]

From-SVN: r78549.2

gcc/ChangeLog

+2004-02-26  Aldy Hernandez  <aldyh@redhat.com>
+
+	* config/rs6000/rs6000.md: Add fixuns_truncsfsi2 and
+	fix_truncsfsi2.
+
+	* config/rs6000/spe.md: Delete spe_efsctuiz.
+	Add spe_fixuns_truncsfsi2.
+	Add spe_fix_truncsfsi2.
+ 
 2004-02-26  Eric Christopher  <echristo@redhat.com>
 
 	* c-lex.c (c_lex_string_translate): New variable.

gcc/config/rs6000/rs6000.md

@@ -4959,6 +4959,20 @@
   "fsel %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
+;; Conversions to and from floating-point.
+
+(define_expand "fixuns_truncsfsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
+  "TARGET_HARD_FLOAT && !TARGET_FPRS"
+  "")
+
+(define_expand "fix_truncsfsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
+  "TARGET_HARD_FLOAT && !TARGET_FPRS"
+  "")
+
 ; For each of these conversions, there is a define_expand, a define_insn
 ; with a '#' template, and a define_split (with C code).  The idea is
 ; to allow constant folding with the template of the define_insn,

gcc/config/rs6000/spe.md

@@ -76,28 +76,19 @@
   "efsdiv %0,%1,%2"
   [(set_attr "type" "vecfdiv")])
 
-(define_insn "spe_efsctuiz"
+(define_insn "spe_fixuns_truncsfsi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (unspec:SI [(match_operand:SF 1 "gpc_reg_operand" "r")] 700))]
+	(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
   "TARGET_HARD_FLOAT && !TARGET_FPRS"
   "efsctuiz %0,%1"
   [(set_attr "type" "fp")])
 
-; These instructions aren't IEEE compliant.  They get some corner cases
-; wrong.  Don't enable them!
-;(define_insn "spe_fixuns_truncsfsi2"
-;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;	(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
-;  "TARGET_HARD_FLOAT && !TARGET_FPRS"
-;  "efsctui %0,%1"
-;  [(set_attr "type" "fp")])
-;
-;(define_insn "spe_fix_truncsfsi2"
-;  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-;	(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
-;  "TARGET_HARD_FLOAT && !TARGET_FPRS"
-;  "efsctsi %0,%1"
-;  [(set_attr "type" "fp")])
+(define_insn "spe_fix_truncsfsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
+  "TARGET_HARD_FLOAT && !TARGET_FPRS"
+  "efsctsiz %0,%1"
+  [(set_attr "type" "fp")])
 
 (define_insn "spe_floatunssisf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=r")