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riscv-gcc-1
Commit d0515b39 by David Edelsohn Committed by David Edelsohn
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rs6000.md (eq<mode>): Use output operand instead of scratch intermediates. 

        * config/rs6000/rs6000.md (eq<mode>): Use output operand instead
        of scratch intermediates.
        (eq<mode>_compare): Same.
        (neg_eq0<mode>): New.
        (neg_eq<mode>): Convert to define_insn_and_split.

From-SVN: r103379
parent 6bd2fcda
Showing with 68 additions and 35 deletions
gcc/ChangeLog
2005-08-23 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (eq<mode>): Use output operand instead
of scratch intermediates.
(eq<mode>_compare): Same.
(neg_eq0<mode>): New.
(neg_eq<mode>): Convert to define_insn_and_split.
2005-08-23 Alan Modra <amodra@bigpond.net.au>
PR target/23070
......
gcc/config/rs6000/rs6000.md
......@@ -11121,58 +11121,60 @@
(define_insn_and_split "*eq<mode>"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
(clobber (match_scratch:GPR 3 "=r"))
(clobber (match_scratch:GPR 4 "=r"))]
(match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
""
"#"
"reload_completed"
[(set (match_dup 3)
(clz:GPR (match_dup 4)))
""
[(set (match_dup 0)
(clz:GPR (match_dup 3)))
(set (match_dup 0)
(lshiftrt:GPR (match_dup 3) (match_dup 5)))]
(lshiftrt:GPR (match_dup 0) (match_dup 4)))]
{
if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
{
/* Use output operand as intermediate. */
operands[3] = operands[0];
if (logical_operand (operands[2], <MODE>mode))
emit_insn (gen_rtx_SET (VOIDmode, operands[4],
emit_insn (gen_rtx_SET (VOIDmode, operands[3],
gen_rtx_XOR (<MODE>mode,
operands[1], operands[2])));
else
emit_insn (gen_rtx_SET (VOIDmode, operands[4],
emit_insn (gen_rtx_SET (VOIDmode, operands[3],
gen_rtx_PLUS (<MODE>mode, operands[1],
negate_rtx (<MODE>mode,
operands[2]))));
}
else
operands[4] = operands[1];
operands[3] = operands[1];
operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
})
(define_insn_and_split "*eq<mode>_compare"
[(set (match_operand:CC 5 "cc_reg_operand" "=y")
[(set (match_operand:CC 3 "cc_reg_operand" "=y")
(compare:CC
(eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
(match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
(const_int 0)))
(set (match_operand:P 0 "gpc_reg_operand" "=r")
(eq:P (match_dup 1) (match_dup 2)))
(clobber (match_scratch:P 3 "=r"))
(clobber (match_scratch:P 4 "=r"))]
(eq:P (match_dup 1) (match_dup 2)))]
""
"#"
"reload_completed"
[(set (match_dup 3)
""
[(set (match_dup 0)
(clz:P (match_dup 4)))
(parallel [(set (match_dup 5)
(compare:CC (lshiftrt:P (match_dup 3) (match_dup 6))
(parallel [(set (match_dup 3)
(compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
(const_int 0)))
(set (match_dup 0)
(lshiftrt:P (match_dup 3) (match_dup 6)))])]
(lshiftrt:P (match_dup 0) (match_dup 5)))])]
{
if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
{
/* Use output operand as intermediate. */
operands[4] = operands[0];
if (logical_operand (operands[2], <MODE>mode))
emit_insn (gen_rtx_SET (VOIDmode, operands[4],
gen_rtx_XOR (<MODE>mode,
......@@ -11186,7 +11188,7 @@
else
operands[4] = operands[1];
operands[6] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
})
;; We have insns of the form shown by the first define_insn below. If
......@@ -11305,19 +11307,42 @@
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))]
"TARGET_32BIT"
"@
xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
{xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "three,two,three,three,three")
(set_attr "length" "12,8,12,12,12")])
(define_insn "*neg_eq0<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
(const_int 0))))]
""
"{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn_and_split "*neg_eq<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
(match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
""
"#"
""
[(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
{
if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
{
/* Use output operand as intermediate. */
operands[3] = operands[0];
if (logical_operand (operands[2], <MODE>mode))
emit_insn (gen_rtx_SET (VOIDmode, operands[3],
gen_rtx_XOR (<MODE>mode,
operands[1], operands[2])));
else
emit_insn (gen_rtx_SET (VOIDmode, operands[3],
gen_rtx_PLUS (<MODE>mode, operands[1],
negate_rtx (<MODE>mode,
operands[2]))));
}
else
operands[3] = operands[1];
})
;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
;; since it nabs/sr is just as fast.
......@@ -12440,7 +12465,7 @@
(const_int 0)))]
"")
(define_insn "*plus_gt<mode>"
(define_insn "*plus_gt0<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=&r")
(plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
(const_int 0))
......
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