Commit d009e1d3 by Kito Cheng

RISC-V: Suppress warning for signed and unsigned integer comparison.

gcc/ChangeLog:

	* config/riscv/riscv.c (riscv_gen_gpr_save_insn): Change type to
	unsigned for i.
	(riscv_gpr_save_operation_p): Change type to unsigned for i and
	len.

(cherry picked from commit 82a3008e56c620008b4575a97e459e2769df54db)
parent 16905340
...@@ -5097,7 +5097,7 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame) ...@@ -5097,7 +5097,7 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame)
gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtx_UNSPEC_VOLATILE (VOIDmode,
gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE); gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE);
for (int i = 1; i < veclen; ++i) for (unsigned i = 1; i < veclen; ++i)
{ {
unsigned regno = gpr_save_reg_order[i]; unsigned regno = gpr_save_reg_order[i];
rtx reg = gen_rtx_REG (Pmode, regno); rtx reg = gen_rtx_REG (Pmode, regno);
...@@ -5125,9 +5125,9 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame) ...@@ -5125,9 +5125,9 @@ riscv_gen_gpr_save_insn (struct riscv_frame_info *frame)
bool bool
riscv_gpr_save_operation_p (rtx op) riscv_gpr_save_operation_p (rtx op)
{ {
HOST_WIDE_INT len = XVECLEN (op, 0); unsigned len = XVECLEN (op, 0);
gcc_assert (len <= ARRAY_SIZE (gpr_save_reg_order)); gcc_assert (len <= ARRAY_SIZE (gpr_save_reg_order));
for (int i = 0; i < len; i++) for (unsigned i = 0; i < len; i++)
{ {
rtx elt = XVECEXP (op, 0, i); rtx elt = XVECEXP (op, 0, i);
if (i == 0) if (i == 0)
......
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