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riscv-gcc-1
Commit d000f0d9 by Shujing Zhao Committed by Nick Clifton
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m32r.c: Use REG_P, MEM_P and CONST_INT_P where applicable. 

        * config/m32r/m32r.c: Use REG_P, MEM_P and CONST_INT_P where
        applicable.
        * config/m32r/m32r.h: Ditto.
        * config/m32r/m32r.md: Ditto.
        * config/m32r/predicates.md: Ditto.

From-SVN: r147899
parent 0c5bf15a
Showing with 89 additions and 82 deletions
gcc/ChangeLog
2009-05-27 Shujing Zhao <pearly.zhao@oracle.com>
* config/m32r/m32r.c: Use REG_P, MEM_P and CONST_INT_P where
applicable.
* config/m32r/m32r.h: Ditto.
* config/m32r/m32r.md: Ditto.
* config/m32r/predicates.md: Ditto.
2009-05-27 Alexandre Oliva <aoliva@redhat.com> 2009-05-27 Alexandre Oliva <aoliva@redhat.com>
* cgraph.c (dump_cgraph_node): Honor -fdump-noaddr. * cgraph.c (dump_cgraph_node): Honor -fdump-noaddr.
2009-05-26 Basile Starynkevitch <basile@starynkevitch.net> 2009-05-26 Basile Starynkevitch <basile@starynkevitch.net>
* doc/plugins.texi * doc/plugins.texi
......
gcc/config/m32r/m32r.c
...@@ -488,7 +488,7 @@ m32r_init_expanders (void) ...@@ -488,7 +488,7 @@ m32r_init_expanders (void)
int int
call_operand (rtx op, enum machine_mode mode) call_operand (rtx op, enum machine_mode mode)
{ {
if (GET_CODE (op) != MEM) if (!MEM_P (op))
return 0; return 0;
op = XEXP (op, 0); op = XEXP (op, 0);
return call_address_operand (op, mode); return call_address_operand (op, mode);
...@@ -563,7 +563,7 @@ addr32_operand (rtx op, enum machine_mode mode) ...@@ -563,7 +563,7 @@ addr32_operand (rtx op, enum machine_mode mode)
else if (GET_CODE (op) == CONST else if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT && CONST_INT_P (XEXP (XEXP (op, 0), 1))
&& ! flag_pic) && ! flag_pic)
sym = XEXP (XEXP (op, 0), 0); sym = XEXP (XEXP (op, 0), 0);
else else
...@@ -632,7 +632,7 @@ easy_df_const (rtx op) ...@@ -632,7 +632,7 @@ easy_df_const (rtx op)
int int
memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{ {
return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG; return REG_P (op) && MEM_P (XEXP (op, 0));
} }
/* Return nonzero if TYPE must be passed by indirect reference. */ /* Return nonzero if TYPE must be passed by indirect reference. */
...@@ -734,7 +734,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) ...@@ -734,7 +734,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
code = EQ; code = EQ;
break; break;
case GT: case GT:
if (GET_CODE (y) == CONST_INT) if (CONST_INT_P (y))
tmp = gen_rtx_PLUS (SImode, y, const1_rtx); tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
else else
emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
...@@ -774,7 +774,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) ...@@ -774,7 +774,7 @@ gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
code = EQ; code = EQ;
break; break;
case GTU: case GTU:
if (GET_CODE (y) == CONST_INT) if (CONST_INT_P (y))
tmp = gen_rtx_PLUS (SImode, y, const1_rtx); tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
else else
emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
...@@ -881,7 +881,7 @@ gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2) ...@@ -881,7 +881,7 @@ gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2)
emit_insn (gen_seq_insn_m32rx (op0, op1, op2)); emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
return true; return true;
} }
if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0) if (CONST_INT_P (op2) && INTVAL (op2) == 0)
{ {
emit_insn (gen_seq_zero_insn (op0, op1)); emit_insn (gen_seq_zero_insn (op0, op1));
return true; return true;
...@@ -894,7 +894,7 @@ gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2) ...@@ -894,7 +894,7 @@ gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2)
return true; return true;
case NE: case NE:
if (GET_CODE (op2) != CONST_INT if (!CONST_INT_P (op2)
|| (INTVAL (op2) != 0 && satisfies_constraint_K (op2))) || (INTVAL (op2) != 0 && satisfies_constraint_K (op2)))
{ {
rtx reg; rtx reg;
...@@ -971,7 +971,7 @@ gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2) ...@@ -971,7 +971,7 @@ gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2)
if (!register_operand (op1, mode)) if (!register_operand (op1, mode))
op1 = force_reg (mode, op1); op1 = force_reg (mode, op1);
if (GET_CODE (op2) == CONST_INT) if (CONST_INT_P (op2))
{ {
HOST_WIDE_INT value = INTVAL (op2); HOST_WIDE_INT value = INTVAL (op2);
if (value >= 2147483647) if (value >= 2147483647)
...@@ -1025,12 +1025,12 @@ gen_split_move_double (rtx operands[]) ...@@ -1025,12 +1025,12 @@ gen_split_move_double (rtx operands[])
alter_subreg (&src); alter_subreg (&src);
start_sequence (); start_sequence ();
if (GET_CODE (dest) == REG) if (REG_P (dest))
{ {
int dregno = REGNO (dest); int dregno = REGNO (dest);
/* Reg = reg. */ /* Reg = reg. */
if (GET_CODE (src) == REG) if (REG_P (src))
{ {
int sregno = REGNO (src); int sregno = REGNO (src);
...@@ -1049,7 +1049,7 @@ gen_split_move_double (rtx operands[]) ...@@ -1049,7 +1049,7 @@ gen_split_move_double (rtx operands[])
} }
/* Reg = constant. */ /* Reg = constant. */
else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE) else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
{ {
rtx words[2]; rtx words[2];
split_double (src, &words[0], &words[1]); split_double (src, &words[0], &words[1]);
...@@ -1063,7 +1063,7 @@ gen_split_move_double (rtx operands[]) ...@@ -1063,7 +1063,7 @@ gen_split_move_double (rtx operands[])
} }
/* Reg = mem. */ /* Reg = mem. */
else if (GET_CODE (src) == MEM) else if (MEM_P (src))
{ {
/* If the high-address word is used in the address, we must load it /* If the high-address word is used in the address, we must load it
last. Otherwise, load it first. */ last. Otherwise, load it first. */
...@@ -1107,7 +1107,7 @@ gen_split_move_double (rtx operands[]) ...@@ -1107,7 +1107,7 @@ gen_split_move_double (rtx operands[])
st r1,r3; st r2,+r3; addi r3,-4 st r1,r3; st r2,+r3; addi r3,-4
which saves 2 bytes and doesn't force longword alignment. */ which saves 2 bytes and doesn't force longword alignment. */
else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG) else if (REG_P (dest) && MEM_P (src))
{ {
emit_insn (gen_rtx_SET (VOIDmode, emit_insn (gen_rtx_SET (VOIDmode,
adjust_address (dest, SImode, 0), adjust_address (dest, SImode, 0),
...@@ -1654,9 +1654,9 @@ m32r_expand_epilogue (void) ...@@ -1654,9 +1654,9 @@ m32r_expand_epilogue (void)
/* If the last insn was a BARRIER, we don't have to write any code /* If the last insn was a BARRIER, we don't have to write any code
because a jump (aka return) was put there. */ because a jump (aka return) was put there. */
if (insn && GET_CODE (insn) == NOTE) if (insn && NOTE_P (insn))
insn = prev_nonnote_insn (insn); insn = prev_nonnote_insn (insn);
if (insn && GET_CODE (insn) == BARRIER) if (insn && BARRIER_P (insn))
noepilogue = TRUE; noepilogue = TRUE;
} }
...@@ -1778,7 +1778,7 @@ m32r_legitimate_pic_operand_p (rtx x) ...@@ -1778,7 +1778,7 @@ m32r_legitimate_pic_operand_p (rtx x)
&& GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
|| GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF) || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
&& (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) && (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return 0; return 0;
return 1; return 1;
...@@ -1857,7 +1857,7 @@ m32r_legitimize_pic_address (rtx orig, rtx reg) ...@@ -1857,7 +1857,7 @@ m32r_legitimize_pic_address (rtx orig, rtx reg)
else else
return orig; return orig;
if (GET_CODE (offset) == CONST_INT) if (CONST_INT_P (offset))
{ {
if (INT16_P (INTVAL (offset))) if (INT16_P (INTVAL (offset)))
return plus_constant (base, INTVAL (offset)); return plus_constant (base, INTVAL (offset));
...@@ -1925,14 +1925,14 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -1925,14 +1925,14 @@ m32r_print_operand (FILE * file, rtx x, int code)
/* The 's' and 'p' codes are used by output_block_move() to /* The 's' and 'p' codes are used by output_block_move() to
indicate post-increment 's'tores and 'p're-increment loads. */ indicate post-increment 's'tores and 'p're-increment loads. */
case 's': case 's':
if (GET_CODE (x) == REG) if (REG_P (x))
fprintf (file, "@+%s", reg_names [REGNO (x)]); fprintf (file, "@+%s", reg_names [REGNO (x)]);
else else
output_operand_lossage ("invalid operand to %%s code"); output_operand_lossage ("invalid operand to %%s code");
return; return;
case 'p': case 'p':
if (GET_CODE (x) == REG) if (REG_P (x))
fprintf (file, "@%s+", reg_names [REGNO (x)]); fprintf (file, "@%s+", reg_names [REGNO (x)]);
else else
output_operand_lossage ("invalid operand to %%p code"); output_operand_lossage ("invalid operand to %%p code");
...@@ -1941,9 +1941,9 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -1941,9 +1941,9 @@ m32r_print_operand (FILE * file, rtx x, int code)
case 'R' : case 'R' :
/* Write second word of DImode or DFmode reference, /* Write second word of DImode or DFmode reference,
register or memory. */ register or memory. */
if (GET_CODE (x) == REG) if (REG_P (x))
fputs (reg_names[REGNO (x)+1], file); fputs (reg_names[REGNO (x)+1], file);
else if (GET_CODE (x) == MEM) else if (MEM_P (x))
{ {
fprintf (file, "@("); fprintf (file, "@(");
/* Handle possible auto-increment. Since it is pre-increment and /* Handle possible auto-increment. Since it is pre-increment and
...@@ -1963,7 +1963,7 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -1963,7 +1963,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
case 'H' : /* High word. */ case 'H' : /* High word. */
case 'L' : /* Low word. */ case 'L' : /* Low word. */
if (GET_CODE (x) == REG) if (REG_P (x))
{ {
/* L = least significant word, H = most significant word. */ /* L = least significant word, H = most significant word. */
if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L')) if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
...@@ -1971,7 +1971,7 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -1971,7 +1971,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
else else
fputs (reg_names[REGNO (x)+1], file); fputs (reg_names[REGNO (x)+1], file);
} }
else if (GET_CODE (x) == CONST_INT else if (CONST_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE) || GET_CODE (x) == CONST_DOUBLE)
{ {
rtx first, second; rtx first, second;
...@@ -2045,7 +2045,7 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -2045,7 +2045,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
case 'U' : case 'U' :
/* ??? wip */ /* ??? wip */
/* Output a load/store with update indicator if appropriate. */ /* Output a load/store with update indicator if appropriate. */
if (GET_CODE (x) == MEM) if (MEM_P (x))
{ {
if (GET_CODE (XEXP (x, 0)) == PRE_INC if (GET_CODE (XEXP (x, 0)) == PRE_INC
|| GET_CODE (XEXP (x, 0)) == PRE_DEC) || GET_CODE (XEXP (x, 0)) == PRE_DEC)
...@@ -2057,7 +2057,7 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -2057,7 +2057,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
case 'N' : case 'N' :
/* Print a constant value negated. */ /* Print a constant value negated. */
if (GET_CODE (x) == CONST_INT) if (CONST_INT_P (x))
output_addr_const (file, GEN_INT (- INTVAL (x))); output_addr_const (file, GEN_INT (- INTVAL (x)));
else else
output_operand_lossage ("invalid operand to %%N code"); output_operand_lossage ("invalid operand to %%N code");
...@@ -2065,7 +2065,7 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -2065,7 +2065,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
case 'X' : case 'X' :
/* Print a const_int in hex. Used in comments. */ /* Print a const_int in hex. Used in comments. */
if (GET_CODE (x) == CONST_INT) if (CONST_INT_P (x))
fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
return; return;
...@@ -2092,21 +2092,21 @@ m32r_print_operand (FILE * file, rtx x, int code) ...@@ -2092,21 +2092,21 @@ m32r_print_operand (FILE * file, rtx x, int code)
addr = XEXP (x, 0); addr = XEXP (x, 0);
if (GET_CODE (addr) == PRE_INC) if (GET_CODE (addr) == PRE_INC)
{ {
if (GET_CODE (XEXP (addr, 0)) != REG) if (!REG_P (XEXP (addr, 0)))
fatal_insn ("pre-increment address is not a register", x); fatal_insn ("pre-increment address is not a register", x);
fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]); fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
} }
else if (GET_CODE (addr) == PRE_DEC) else if (GET_CODE (addr) == PRE_DEC)
{ {
if (GET_CODE (XEXP (addr, 0)) != REG) if (!REG_P (XEXP (addr, 0)))
fatal_insn ("pre-decrement address is not a register", x); fatal_insn ("pre-decrement address is not a register", x);
fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]); fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
} }
else if (GET_CODE (addr) == POST_INC) else if (GET_CODE (addr) == POST_INC)
{ {
if (GET_CODE (XEXP (addr, 0)) != REG) if (!REG_P (XEXP (addr, 0)))
fatal_insn ("post-increment address is not a register", x); fatal_insn ("post-increment address is not a register", x);
fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]); fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
...@@ -2156,13 +2156,13 @@ m32r_print_operand_address (FILE * file, rtx addr) ...@@ -2156,13 +2156,13 @@ m32r_print_operand_address (FILE * file, rtx addr)
break; break;
case PLUS : case PLUS :
if (GET_CODE (XEXP (addr, 0)) == CONST_INT) if (CONST_INT_P (XEXP (addr, 0)))
offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) else if (CONST_INT_P (XEXP (addr, 1)))
offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
else else
base = XEXP (addr, 0), index = XEXP (addr, 1); base = XEXP (addr, 0), index = XEXP (addr, 1);
if (GET_CODE (base) == REG) if (REG_P (base))
{ {
/* Print the offset first (if present) to conform to the manual. */ /* Print the offset first (if present) to conform to the manual. */
if (index == 0) if (index == 0)
...@@ -2172,7 +2172,7 @@ m32r_print_operand_address (FILE * file, rtx addr) ...@@ -2172,7 +2172,7 @@ m32r_print_operand_address (FILE * file, rtx addr)
fputs (reg_names[REGNO (base)], file); fputs (reg_names[REGNO (base)], file);
} }
/* The chip doesn't support this, but left in for generality. */ /* The chip doesn't support this, but left in for generality. */
else if (GET_CODE (index) == REG) else if (REG_P (index))
fprintf (file, "%s,%s", fprintf (file, "%s,%s",
reg_names[REGNO (base)], reg_names[REGNO (index)]); reg_names[REGNO (base)], reg_names[REGNO (index)]);
/* Not sure this can happen, but leave in for now. */ /* Not sure this can happen, but leave in for now. */
...@@ -2187,7 +2187,7 @@ m32r_print_operand_address (FILE * file, rtx addr) ...@@ -2187,7 +2187,7 @@ m32r_print_operand_address (FILE * file, rtx addr)
} }
else if (GET_CODE (base) == LO_SUM) else if (GET_CODE (base) == LO_SUM)
{ {
gcc_assert (!index && GET_CODE (XEXP (base, 0)) == REG); gcc_assert (!index && REG_P (XEXP (base, 0)));
if (small_data_operand (XEXP (base, 1), VOIDmode)) if (small_data_operand (XEXP (base, 1), VOIDmode))
fputs ("sda(", file); fputs ("sda(", file);
else else
...@@ -2201,7 +2201,7 @@ m32r_print_operand_address (FILE * file, rtx addr) ...@@ -2201,7 +2201,7 @@ m32r_print_operand_address (FILE * file, rtx addr)
break; break;
case LO_SUM : case LO_SUM :
if (GET_CODE (XEXP (addr, 0)) != REG) if (!REG_P (XEXP (addr, 0)))
fatal_insn ("lo_sum not of register", addr); fatal_insn ("lo_sum not of register", addr);
if (small_data_operand (XEXP (addr, 1), VOIDmode)) if (small_data_operand (XEXP (addr, 1), VOIDmode))
fputs ("sda(", file); fputs ("sda(", file);
...@@ -2236,8 +2236,8 @@ int ...@@ -2236,8 +2236,8 @@ int
zero_and_one (rtx operand1, rtx operand2) zero_and_one (rtx operand1, rtx operand2)
{ {
return return
GET_CODE (operand1) == CONST_INT CONST_INT_P (operand1)
&& GET_CODE (operand2) == CONST_INT && CONST_INT_P (operand2)
&& ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1)) && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0))); ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
} }
...@@ -2257,7 +2257,7 @@ emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED) ...@@ -2257,7 +2257,7 @@ emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
buffer [0] = 0; buffer [0] = 0;
/* Destination must be a register. */ /* Destination must be a register. */
gcc_assert (GET_CODE (operands [0]) == REG); gcc_assert (REG_P (operands [0]));
gcc_assert (conditional_move_operand (operands [2], SImode)); gcc_assert (conditional_move_operand (operands [2], SImode));
gcc_assert (conditional_move_operand (operands [3], SImode)); gcc_assert (conditional_move_operand (operands [3], SImode));
...@@ -2291,13 +2291,13 @@ m32r_not_same_reg (rtx a, rtx b) ...@@ -2291,13 +2291,13 @@ m32r_not_same_reg (rtx a, rtx b)
while (GET_CODE (a) == SUBREG) while (GET_CODE (a) == SUBREG)
a = SUBREG_REG (a); a = SUBREG_REG (a);
if (GET_CODE (a) == REG) if (REG_P (a))
reg_a = REGNO (a); reg_a = REGNO (a);
while (GET_CODE (b) == SUBREG) while (GET_CODE (b) == SUBREG)
b = SUBREG_REG (b); b = SUBREG_REG (b);
if (GET_CODE (b) == REG) if (REG_P (b))
reg_b = REGNO (b); reg_b = REGNO (b);
return reg_a != reg_b; return reg_a != reg_b;
...@@ -2361,7 +2361,7 @@ m32r_expand_block_move (rtx operands[]) ...@@ -2361,7 +2361,7 @@ m32r_expand_block_move (rtx operands[])
rtx orig_src = operands[1]; rtx orig_src = operands[1];
rtx bytes_rtx = operands[2]; rtx bytes_rtx = operands[2];
rtx align_rtx = operands[3]; rtx align_rtx = operands[3];
int constp = GET_CODE (bytes_rtx) == CONST_INT; int constp = CONST_INT_P (bytes_rtx);
HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0; HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
int align = INTVAL (align_rtx); int align = INTVAL (align_rtx);
int leftover; int leftover;
......
gcc/config/m32r/m32r.h
...@@ -1059,7 +1059,7 @@ L2: .word STATIC ...@@ -1059,7 +1059,7 @@ L2: .word STATIC
#define CONSTANT_ADDRESS_P(X) \ #define CONSTANT_ADDRESS_P(X) \
( GET_CODE (X) == LABEL_REF \ ( GET_CODE (X) == LABEL_REF \
|| GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST_INT \ || CONST_INT_P (X) \
|| (GET_CODE (X) == CONST \ || (GET_CODE (X) == CONST \
&& ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
...@@ -1073,7 +1073,7 @@ L2: .word STATIC ...@@ -1073,7 +1073,7 @@ L2: .word STATIC
(! (GET_CODE (X) == CONST \ (! (GET_CODE (X) == CONST \
&& GET_CODE (XEXP (X, 0)) == PLUS \ && GET_CODE (XEXP (X, 0)) == PLUS \
&& (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \ && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
&& (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767)) && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
...@@ -1120,7 +1120,7 @@ L2: .word STATIC ...@@ -1120,7 +1120,7 @@ L2: .word STATIC
/* Local to this file. */ /* Local to this file. */
#define RTX_OK_FOR_OFFSET_P(X) \ #define RTX_OK_FOR_OFFSET_P(X) \
(GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X))) (CONST_INT_P (X) && INT16_P (INTVAL (X)))
/* Local to this file. */ /* Local to this file. */
#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \ #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
...@@ -1142,7 +1142,7 @@ L2: .word STATIC ...@@ -1142,7 +1142,7 @@ L2: .word STATIC
#define LOAD_POSTINC_P(MODE, X) \ #define LOAD_POSTINC_P(MODE, X) \
(((MODE) == SImode || (MODE) == SFmode) \ (((MODE) == SImode || (MODE) == SFmode) \
&& GET_CODE (X) == POST_INC \ && GET_CODE (X) == POST_INC \
&& GET_CODE (XEXP (X, 0)) == REG \ && REG_P (XEXP (X, 0)) \
&& RTX_OK_FOR_BASE_P (XEXP (X, 0))) && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
/* Local to this file. */ /* Local to this file. */
...@@ -1150,7 +1150,7 @@ L2: .word STATIC ...@@ -1150,7 +1150,7 @@ L2: .word STATIC
#define STORE_PREINC_PREDEC_P(MODE, X) \ #define STORE_PREINC_PREDEC_P(MODE, X) \
(((MODE) == SImode || (MODE) == SFmode) \ (((MODE) == SImode || (MODE) == SFmode) \
&& (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \ && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
&& GET_CODE (XEXP (X, 0)) == REG \ && REG_P (XEXP (X, 0)) \
&& RTX_OK_FOR_BASE_P (XEXP (X, 0))) && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
......
gcc/config/m32r/m32r.md
...@@ -250,7 +250,7 @@ ...@@ -250,7 +250,7 @@
/* Everything except mem = const or mem = mem can be done easily. /* Everything except mem = const or mem = mem can be done easily.
Objects in the small data area are handled too. */ Objects in the small data area are handled too. */
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]); operands[1] = force_reg (QImode, operands[1]);
}") }")
...@@ -289,7 +289,7 @@ ...@@ -289,7 +289,7 @@
/* Everything except mem = const or mem = mem can be done easily. */ /* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
}") }")
...@@ -341,7 +341,7 @@ ...@@ -341,7 +341,7 @@
/* Everything except mem = const or mem = mem can be done easily. */ /* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
/* Small Data Area reference? */ /* Small Data Area reference? */
...@@ -367,7 +367,7 @@ ...@@ -367,7 +367,7 @@
"register_operand (operands[0], SImode) || register_operand (operands[1], SImode)" "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
"* "*
{ {
if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG) if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
{ {
switch (GET_CODE (operands[1])) switch (GET_CODE (operands[1]))
{ {
...@@ -409,8 +409,8 @@ ...@@ -409,8 +409,8 @@
} }
} }
else if (GET_CODE (operands[0]) == MEM else if (MEM_P (operands[0])
&& (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)) && (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
{ {
if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx) && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
...@@ -585,7 +585,7 @@ ...@@ -585,7 +585,7 @@
/* Everything except mem = const or mem = mem can be done easily. */ /* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]); operands[1] = force_reg (DImode, operands[1]);
}") }")
...@@ -626,7 +626,7 @@ ...@@ -626,7 +626,7 @@
/* Everything except mem = const or mem = mem can be done easily. */ /* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]); operands[1] = force_reg (SFmode, operands[1]);
}") }")
...@@ -678,7 +678,7 @@ ...@@ -678,7 +678,7 @@
/* Everything except mem = const or mem = mem can be done easily. */ /* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]); operands[1] = force_reg (DFmode, operands[1]);
}") }")
...@@ -1036,7 +1036,7 @@ ...@@ -1036,7 +1036,7 @@
&& satisfies_constraint_I (operands[2])) && satisfies_constraint_I (operands[2]))
return \"#\"; return \"#\";
else if (GET_CODE (operands[2]) == CONST_INT) else if (CONST_INT_P (operands[2]))
return \"and3 %0,%1,%#%X2\"; return \"and3 %0,%1,%#%X2\";
return \"and %0,%2\"; return \"and %0,%2\";
...@@ -1067,7 +1067,7 @@ ...@@ -1067,7 +1067,7 @@
&& satisfies_constraint_I (operands[2])) && satisfies_constraint_I (operands[2]))
return \"#\"; return \"#\";
else if (GET_CODE (operands[2]) == CONST_INT) else if (CONST_INT_P (operands[2]))
return \"or3 %0,%1,%#%X2\"; return \"or3 %0,%1,%#%X2\";
return \"or %0,%2\"; return \"or %0,%2\";
...@@ -1098,7 +1098,7 @@ ...@@ -1098,7 +1098,7 @@
&& satisfies_constraint_I (operands[2])) && satisfies_constraint_I (operands[2]))
return \"#\"; return \"#\";
else if (GET_CODE (operands[2]) == CONST_INT) else if (CONST_INT_P (operands[2]))
return \"xor3 %0,%1,%#%X2\"; return \"xor3 %0,%1,%#%X2\";
return \"xor %0,%2\"; return \"xor %0,%2\";
...@@ -1588,7 +1588,7 @@ ...@@ -1588,7 +1588,7 @@
rtx op3 = operands[3]; rtx op3 = operands[3];
HOST_WIDE_INT value; HOST_WIDE_INT value;
if (GET_CODE (op2) == REG && GET_CODE (op3) == REG if (REG_P (op2) && REG_P (op3)
&& REGNO (op2) == REGNO (op3)) && REGNO (op2) == REGNO (op3))
{ {
op1 = operands[2]; op1 = operands[2];
...@@ -1596,7 +1596,7 @@ ...@@ -1596,7 +1596,7 @@
} }
start_sequence (); start_sequence ();
if (GET_CODE (op1) == REG && GET_CODE (op3) == REG if (REG_P (op1) && REG_P (op3)
&& REGNO (op1) != REGNO (op3)) && REGNO (op1) != REGNO (op3))
{ {
emit_move_insn (op3, op1); emit_move_insn (op3, op1);
......
gcc/config/m32r/predicates.md
...@@ -22,10 +22,10 @@ ...@@ -22,10 +22,10 @@
(define_predicate "reg_or_zero_operand" (define_predicate "reg_or_zero_operand"
(match_code "reg,subreg,const_int") (match_code "reg,subreg,const_int")
{ {
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG) if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode); return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
return INTVAL (op) == 0; return INTVAL (op) == 0;
...@@ -75,11 +75,11 @@ ...@@ -75,11 +75,11 @@
return FALSE; return FALSE;
x = XEXP (op, 0); x = XEXP (op, 0);
if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM) if (!REG_P (x) || REGNO (x) != CARRY_REGNUM)
return FALSE; return FALSE;
x = XEXP (op, 1); x = XEXP (op, 1);
if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0) if (!CONST_INT_P (x) || INTVAL (x) != 0)
return FALSE; return FALSE;
return TRUE; return TRUE;
...@@ -119,7 +119,7 @@ ...@@ -119,7 +119,7 @@
case SUBREG : case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a /* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */ pseudo-reg and is now a stack slot. */
if (GET_CODE (SUBREG_REG (op)) == MEM) if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode); return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else else
return register_operand (op, mode); return register_operand (op, mode);
...@@ -175,7 +175,7 @@ ...@@ -175,7 +175,7 @@
case SUBREG : case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a /* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */ pseudo-reg and is now a stack slot. */
if (GET_CODE (SUBREG_REG (op)) == MEM) if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode); return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else else
return register_operand (op, mode); return register_operand (op, mode);
...@@ -205,7 +205,7 @@ ...@@ -205,7 +205,7 @@
case SUBREG : case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a /* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */ pseudo-reg and is now a stack slot. */
if (GET_CODE (SUBREG_REG (op)) == MEM) if (MEM_P (SUBREG_REG (op)))
return move_double_src_operand (SUBREG_REG (op), mode); return move_double_src_operand (SUBREG_REG (op), mode);
else else
return register_operand (op, mode); return register_operand (op, mode);
...@@ -226,7 +226,7 @@ ...@@ -226,7 +226,7 @@
(define_predicate "two_insn_const_operand" (define_predicate "two_insn_const_operand"
(match_code "const_int") (match_code "const_int")
{ {
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
if (satisfies_constraint_J (op) if (satisfies_constraint_J (op)
|| satisfies_constraint_M (op) || satisfies_constraint_M (op)
...@@ -257,7 +257,7 @@ ...@@ -257,7 +257,7 @@
(define_predicate "int8_operand" (define_predicate "int8_operand"
(match_code "const_int") (match_code "const_int")
{ {
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
return satisfies_constraint_I (op); return satisfies_constraint_I (op);
}) })
...@@ -267,7 +267,7 @@ ...@@ -267,7 +267,7 @@
(define_predicate "uint16_operand" (define_predicate "uint16_operand"
(match_code "const_int") (match_code "const_int")
{ {
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
return satisfies_constraint_K (op); return satisfies_constraint_K (op);
}) })
...@@ -277,9 +277,9 @@ ...@@ -277,9 +277,9 @@
(define_predicate "reg_or_int16_operand" (define_predicate "reg_or_int16_operand"
(match_code "reg,subreg,const_int") (match_code "reg,subreg,const_int")
{ {
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG) if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode); return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
return satisfies_constraint_J (op); return satisfies_constraint_J (op);
}) })
...@@ -289,9 +289,9 @@ ...@@ -289,9 +289,9 @@
(define_predicate "reg_or_uint16_operand" (define_predicate "reg_or_uint16_operand"
(match_code "reg,subreg,const_int") (match_code "reg,subreg,const_int")
{ {
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG) if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode); return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
return satisfies_constraint_K (op); return satisfies_constraint_K (op);
}) })
...@@ -302,9 +302,9 @@ ...@@ -302,9 +302,9 @@
(define_predicate "reg_or_cmp_int16_operand" (define_predicate "reg_or_cmp_int16_operand"
(match_code "reg,subreg,const_int") (match_code "reg,subreg,const_int")
{ {
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG) if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode); return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
return satisfies_constraint_P (op); return satisfies_constraint_P (op);
}) })
...@@ -319,10 +319,10 @@ ...@@ -319,10 +319,10 @@
{ {
HOST_WIDE_INT value; HOST_WIDE_INT value;
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG) if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode); return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
value = INTVAL (op); value = INTVAL (op);
...@@ -335,7 +335,7 @@ ...@@ -335,7 +335,7 @@
(define_predicate "cmp_int16_operand" (define_predicate "cmp_int16_operand"
(match_code "const_int") (match_code "const_int")
{ {
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
return satisfies_constraint_P (op); return satisfies_constraint_P (op);
}) })
...@@ -384,7 +384,7 @@ ...@@ -384,7 +384,7 @@
(define_predicate "small_insn_p" (define_predicate "small_insn_p"
(match_code "insn,call_insn,jump_insn") (match_code "insn,call_insn,jump_insn")
{ {
if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0) if (CONST_INT_P (op) && INTVAL (op) == 0)
return 1; return 1;
if (! INSN_P (op)) if (! INSN_P (op))
...@@ -399,7 +399,7 @@ ...@@ -399,7 +399,7 @@
(define_predicate "m32r_block_immediate_operand" (define_predicate "m32r_block_immediate_operand"
(match_code "const_int") (match_code "const_int")
{ {
if (GET_CODE (op) != CONST_INT if (!CONST_INT_P (op)
|| INTVAL (op) > MAX_MOVE_BYTES || INTVAL (op) > MAX_MOVE_BYTES
|| INTVAL (op) <= 0) || INTVAL (op) <= 0)
return 0; return 0;
......
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