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riscv-gcc-1
Commit d000f0d9 by Shujing Zhao Committed by Nick Clifton
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m32r.c: Use REG_P, MEM_P and CONST_INT_P where applicable. 

        * config/m32r/m32r.c: Use REG_P, MEM_P and CONST_INT_P where
        applicable.
        * config/m32r/m32r.h: Ditto.
        * config/m32r/m32r.md: Ditto.
        * config/m32r/predicates.md: Ditto.

From-SVN: r147899
parent 0c5bf15a
Showing with 89 additions and 82 deletions
gcc/ChangeLog
2009-05-27 Shujing Zhao <pearly.zhao@oracle.com>
* config/m32r/m32r.c: Use REG_P, MEM_P and CONST_INT_P where
applicable.
* config/m32r/m32r.h: Ditto.
* config/m32r/m32r.md: Ditto.
* config/m32r/predicates.md: Ditto.
2009-05-27 Alexandre Oliva <aoliva@redhat.com>
* cgraph.c (dump_cgraph_node): Honor -fdump-noaddr.
2009-05-26 Basile Starynkevitch <basile@starynkevitch.net>
* doc/plugins.texi
......
gcc/config/m32r/m32r.h
......@@ -1059,7 +1059,7 @@ L2: .word STATIC
#define CONSTANT_ADDRESS_P(X) \
( GET_CODE (X) == LABEL_REF \
|| GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST_INT \
|| CONST_INT_P (X) \
|| (GET_CODE (X) == CONST \
&& ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
......@@ -1073,7 +1073,7 @@ L2: .word STATIC
(! (GET_CODE (X) == CONST \
&& GET_CODE (XEXP (X, 0)) == PLUS \
&& (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
&& CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
&& (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
......@@ -1120,7 +1120,7 @@ L2: .word STATIC
/* Local to this file. */
#define RTX_OK_FOR_OFFSET_P(X) \
(GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
(CONST_INT_P (X) && INT16_P (INTVAL (X)))
/* Local to this file. */
#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
......@@ -1142,7 +1142,7 @@ L2: .word STATIC
#define LOAD_POSTINC_P(MODE, X) \
(((MODE) == SImode || (MODE) == SFmode) \
&& GET_CODE (X) == POST_INC \
&& GET_CODE (XEXP (X, 0)) == REG \
&& REG_P (XEXP (X, 0)) \
&& RTX_OK_FOR_BASE_P (XEXP (X, 0)))
/* Local to this file. */
......@@ -1150,7 +1150,7 @@ L2: .word STATIC
#define STORE_PREINC_PREDEC_P(MODE, X) \
(((MODE) == SImode || (MODE) == SFmode) \
&& (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
&& GET_CODE (XEXP (X, 0)) == REG \
&& REG_P (XEXP (X, 0)) \
&& RTX_OK_FOR_BASE_P (XEXP (X, 0)))
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
......
gcc/config/m32r/m32r.md
......@@ -250,7 +250,7 @@
/* Everything except mem = const or mem = mem can be done easily.
Objects in the small data area are handled too. */
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]);
}")
......@@ -289,7 +289,7 @@
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
}")
......@@ -341,7 +341,7 @@
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]);
/* Small Data Area reference? */
......@@ -367,7 +367,7 @@
"register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
"*
{
if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG)
if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
{
switch (GET_CODE (operands[1]))
{
......@@ -409,8 +409,8 @@
}
}
else if (GET_CODE (operands[0]) == MEM
&& (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))
else if (MEM_P (operands[0])
&& (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
{
if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
......@@ -585,7 +585,7 @@
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]);
}")
......@@ -626,7 +626,7 @@
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]);
}")
......@@ -678,7 +678,7 @@
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]);
}")
......@@ -1036,7 +1036,7 @@
&& satisfies_constraint_I (operands[2]))
return \"#\";
else if (GET_CODE (operands[2]) == CONST_INT)
else if (CONST_INT_P (operands[2]))
return \"and3 %0,%1,%#%X2\";
return \"and %0,%2\";
......@@ -1067,7 +1067,7 @@
&& satisfies_constraint_I (operands[2]))
return \"#\";
else if (GET_CODE (operands[2]) == CONST_INT)
else if (CONST_INT_P (operands[2]))
return \"or3 %0,%1,%#%X2\";
return \"or %0,%2\";
......@@ -1098,7 +1098,7 @@
&& satisfies_constraint_I (operands[2]))
return \"#\";
else if (GET_CODE (operands[2]) == CONST_INT)
else if (CONST_INT_P (operands[2]))
return \"xor3 %0,%1,%#%X2\";
return \"xor %0,%2\";
......@@ -1588,7 +1588,7 @@
rtx op3 = operands[3];
HOST_WIDE_INT value;
if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
if (REG_P (op2) && REG_P (op3)
&& REGNO (op2) == REGNO (op3))
{
op1 = operands[2];
......@@ -1596,7 +1596,7 @@
}
start_sequence ();
if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
if (REG_P (op1) && REG_P (op3)
&& REGNO (op1) != REGNO (op3))
{
emit_move_insn (op3, op1);
......
gcc/config/m32r/predicates.md
......@@ -22,10 +22,10 @@
(define_predicate "reg_or_zero_operand"
(match_code "reg,subreg,const_int")
{
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
return INTVAL (op) == 0;
......@@ -75,11 +75,11 @@
return FALSE;
x = XEXP (op, 0);
if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
if (!REG_P (x) || REGNO (x) != CARRY_REGNUM)
return FALSE;
x = XEXP (op, 1);
if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
if (!CONST_INT_P (x) || INTVAL (x) != 0)
return FALSE;
return TRUE;
......@@ -119,7 +119,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
if (GET_CODE (SUBREG_REG (op)) == MEM)
if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else
return register_operand (op, mode);
......@@ -175,7 +175,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
if (GET_CODE (SUBREG_REG (op)) == MEM)
if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else
return register_operand (op, mode);
......@@ -205,7 +205,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
if (GET_CODE (SUBREG_REG (op)) == MEM)
if (MEM_P (SUBREG_REG (op)))
return move_double_src_operand (SUBREG_REG (op), mode);
else
return register_operand (op, mode);
......@@ -226,7 +226,7 @@
(define_predicate "two_insn_const_operand"
(match_code "const_int")
{
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
if (satisfies_constraint_J (op)
|| satisfies_constraint_M (op)
......@@ -257,7 +257,7 @@
(define_predicate "int8_operand"
(match_code "const_int")
{
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
return satisfies_constraint_I (op);
})
......@@ -267,7 +267,7 @@
(define_predicate "uint16_operand"
(match_code "const_int")
{
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
return satisfies_constraint_K (op);
})
......@@ -277,9 +277,9 @@
(define_predicate "reg_or_int16_operand"
(match_code "reg,subreg,const_int")
{
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
return satisfies_constraint_J (op);
})
......@@ -289,9 +289,9 @@
(define_predicate "reg_or_uint16_operand"
(match_code "reg,subreg,const_int")
{
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
return satisfies_constraint_K (op);
})
......@@ -302,9 +302,9 @@
(define_predicate "reg_or_cmp_int16_operand"
(match_code "reg,subreg,const_int")
{
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
return satisfies_constraint_P (op);
})
......@@ -319,10 +319,10 @@
{
HOST_WIDE_INT value;
if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode);
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
value = INTVAL (op);
......@@ -335,7 +335,7 @@
(define_predicate "cmp_int16_operand"
(match_code "const_int")
{
if (GET_CODE (op) != CONST_INT)
if (!CONST_INT_P (op))
return 0;
return satisfies_constraint_P (op);
})
......@@ -384,7 +384,7 @@
(define_predicate "small_insn_p"
(match_code "insn,call_insn,jump_insn")
{
if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
if (CONST_INT_P (op) && INTVAL (op) == 0)
return 1;
if (! INSN_P (op))
......@@ -399,7 +399,7 @@
(define_predicate "m32r_block_immediate_operand"
(match_code "const_int")
{
if (GET_CODE (op) != CONST_INT
if (!CONST_INT_P (op)
|| INTVAL (op) > MAX_MOVE_BYTES
|| INTVAL (op) <= 0)
return 0;
......
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