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Commit cfc72af0 by Uros Bizjak Committed by Uros Bizjak
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i386.md (*load_tp_<mode>): Redefine as define_insn_and_split. 

	* config/i386/i386.md (*load_tp_<mode>): Redefine as
	define_insn_and_split.  Split to a memory load from 0 in
	DEFAULT_TLS_SEG_REG address space.  Merge with *load_tp_x32
	using PTR mode iterator.
	(*load_tp_x32_zext"): Redefine as define_insn_and_split.
	Split to a memory load from 0 in DEFAULT_TLS_SEG_REG address space.
	(*add_tp_<mode>): Redefine as define_insn_and_split.
	Split to an add with a memory load from 0 in DEFAULT_TLS_SEG_REG
	address space.  Merge with *add_tp_x32 using PTR mode iterator.
	(*add_tp_x32_zext"): Redefine as define_insn_and_split.
	Split to an add with a  memory load from 0 in
	DEFAULT_TLS_SEG_REG address space.

From-SVN: r251075
parent 04c4bb30
Showing with 72 additions and 61 deletions
gcc/ChangeLog
2017-08-13 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*load_tp_<mode>): Redefine as
define_insn_and_split. Split to a memory load from 0 in
DEFAULT_TLS_SEG_REG address space. Merge with *load_tp_x32
using PTR mode iterator.
(*load_tp_x32_zext"): Redefine as define_insn_and_split.
Split to a memory load from 0 in DEFAULT_TLS_SEG_REG address space.
(*add_tp_<mode>): Redefine as define_insn_and_split.
Split to an add with a memory load from 0 in DEFAULT_TLS_SEG_REG
address space. Merge with *add_tp_x32 using PTR mode iterator.
(*add_tp_x32_zext"): Redefine as define_insn_and_split.
Split to an add with a memory load from 0 in
DEFAULT_TLS_SEG_REG address space.
2017-08-12 Andrew Pinski <apinski@cavium.com> 2017-08-12 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-option-extensions.def (rdma): * config/aarch64/aarch64-option-extensions.def (rdma):
......
gcc/config/i386/i386.md
...@@ -13773,82 +13773,78 @@ ...@@ -13773,82 +13773,78 @@
(clobber (match_dup 5)) (clobber (match_dup 5))
(clobber (reg:CC FLAGS_REG))])]) (clobber (reg:CC FLAGS_REG))])])
;; Segment register for the thread base ptr load
(define_mode_attr tp_seg [(SI "gs") (DI "fs")])
;; Load and add the thread base pointer from %<tp_seg>:0. ;; Load and add the thread base pointer from %<tp_seg>:0.
(define_insn "*load_tp_x32" (define_insn_and_split "*load_tp_<mode>"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:PTR 0 "register_operand" "=r")
(unspec:SI [(const_int 0)] UNSPEC_TP))] (unspec:PTR [(const_int 0)] UNSPEC_TP))]
"TARGET_X32" ""
"mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" "#"
[(set_attr "type" "imov") ""
(set_attr "modrm" "0") [(set (match_dup 0)
(set_attr "length" "7") (match_dup 1))]
(set_attr "memory" "load") {
(set_attr "imm_disp" "false")]) addr_space_t as = DEFAULT_TLS_SEG_REG;
(define_insn "*load_tp_x32_zext" operands[1] = gen_const_mem (<MODE>mode, const0_rtx);
set_mem_addr_space (operands[1], as);
})
(define_insn_and_split "*load_tp_x32_zext"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))] (zero_extend:DI
(unspec:SI [(const_int 0)] UNSPEC_TP)))]
"TARGET_X32" "TARGET_X32"
"mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" "#"
[(set_attr "type" "imov") ""
(set_attr "modrm" "0") [(set (match_dup 0)
(set_attr "length" "7") (zero_extend:DI (match_dup 1)))]
(set_attr "memory" "load") {
(set_attr "imm_disp" "false")]) addr_space_t as = DEFAULT_TLS_SEG_REG;
(define_insn "*load_tp_<mode>" operands[1] = gen_const_mem (SImode, const0_rtx);
[(set (match_operand:P 0 "register_operand" "=r") set_mem_addr_space (operands[1], as);
(unspec:P [(const_int 0)] UNSPEC_TP))] })
"!TARGET_X32"
"mov{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
[(set_attr "type" "imov")
(set_attr "modrm" "0")
(set_attr "length" "7")
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
(define_insn "*add_tp_x32" (define_insn_and_split "*add_tp_<mode>"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:PTR 0 "register_operand" "=r")
(plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) (plus:PTR
(match_operand:SI 1 "register_operand" "0"))) (unspec:PTR [(const_int 0)] UNSPEC_TP)
(match_operand:PTR 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))] (clobber (reg:CC FLAGS_REG))]
"TARGET_X32" ""
"add{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" "#"
[(set_attr "type" "alu") ""
(set_attr "modrm" "0") [(parallel
(set_attr "length" "7") [(set (match_dup 0)
(set_attr "memory" "load") (plus:PTR (match_dup 1) (match_dup 2)))
(set_attr "imm_disp" "false")]) (clobber (reg:CC FLAGS_REG))])]
{
addr_space_t as = DEFAULT_TLS_SEG_REG;
operands[2] = gen_const_mem (<MODE>mode, const0_rtx);
set_mem_addr_space (operands[2], as);
})
(define_insn "*add_tp_x32_zext" (define_insn_and_split "*add_tp_x32_zext"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (zero_extend:DI
(plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
(match_operand:SI 1 "register_operand" "0")))) (match_operand:SI 1 "register_operand" "0"))))
(clobber (reg:CC FLAGS_REG))] (clobber (reg:CC FLAGS_REG))]
"TARGET_X32" "TARGET_X32"
"add{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" "#"
[(set_attr "type" "alu") ""
(set_attr "modrm" "0") [(parallel
(set_attr "length" "7") [(set (match_dup 0)
(set_attr "memory" "load") (zero_extend:DI
(set_attr "imm_disp" "false")]) (plus:SI (match_dup 1) (match_dup 2))))
(clobber (reg:CC FLAGS_REG))])]
{
addr_space_t as = DEFAULT_TLS_SEG_REG;
(define_insn "*add_tp_<mode>" operands[2] = gen_const_mem (SImode, const0_rtx);
[(set (match_operand:P 0 "register_operand" "=r") set_mem_addr_space (operands[2], as);
(plus:P (unspec:P [(const_int 0)] UNSPEC_TP) })
(match_operand:P 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_X32"
"add{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
[(set_attr "type" "alu")
(set_attr "modrm" "0")
(set_attr "length" "7")
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
;; The Sun linker took the AMD64 TLS spec literally and can only handle ;; The Sun linker took the AMD64 TLS spec literally and can only handle
;; %rax as destination of the initial executable code sequence. ;; %rax as destination of the initial executable code sequence.
......
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