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riscv-gcc-1
Commit cfb557c4 by Richard Kenner
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(define_attr): Expand list of instruction attributes. 

(define_function_unit): Compute delay information based upon processor type
and expand functional unit types.
(mulsi3, divsi3, divmodsi4, divsf3, divdf3, muldf3, movsf): Use expanded
attributes.
(load with update): Likewise.

From-SVN: r5284
parent 5248c961
Showing with 170 additions and 40 deletions
gcc/config/rs6000/rs6000.md
......@@ -22,7 +22,7 @@
;; Define an insn type attribute. This is used in function unit delay
;; computations.
(define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr,branch"
(define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtlr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt"
(const_string "integer"))
;; Length (in bytes).
......@@ -36,24 +36,152 @@
(const_int 12))
(const_int 4)))
;; Memory delivers its result in two cycles.
(define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
;; We consider floating-point insns to deliver their result in two cycles
;; to try to intersperse integer and FP operations.
(define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
;; Most integer comparisons are ready in four cycles (a stall of three).
(define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
;; Some integer comparisons aren't ready for five cycles (a stall of four).
(define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
;; Floating-point comparisons take eight cycles.
(define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
;; Branches on LR cannot be done until five cycles after LR is set.
(define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0)
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
(define_attr "cpu" "rios,rios2,ppc601,ppc603,ppc604,ppc620"
(const (symbol_ref "rs6000_cpu_attr")))
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "load")
(eq_attr "cpu" "ppc603,ppc604,ppc620"))
2 0)
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "ppc603,ppc604,ppc620"))
2 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "load")
(eq_attr "cpu" "rios,rios2"))
2 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "fpload")
(eq_attr "cpu" "rios,rios2"))
3 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "rios,rios2"))
3 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
5 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "rios,rios2"))
19 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
36 0)
(define_function_unit "bpu" 1 0
(eq_attr "type" "compare")
4 0)
(define_function_unit "bpu" 1 0
(eq_attr "type" "delayed_compare")
5 0)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "rios,rios2"))
8 0)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "fpcompare")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
4 0)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtlr")
(eq_attr "cpu" "rios,rios2"))
5 0)
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtlr")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
4 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "rios"))
2 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
4 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "rios"))
2 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
5 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "rios"))
19 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
17 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "rios"))
19 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
31 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "ppc603,ppc604,ppc620"))
31 0)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "ppc603,ppc604,ppc620"))
31 0)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "fp")
(eq_attr "cpu" "rios2"))
2 0)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dmul")
(eq_attr "cpu" "rios2"))
2 0)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "sdiv")
(eq_attr "cpu" "rios2"))
19 0)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ddiv")
(eq_attr "cpu" "rios2"))
19 0)
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
......@@ -453,7 +581,8 @@
""
"@
muls %0,%1,%2
muli %0,%1,%2")
muli %0,%1,%2"
[(set_attr "type" "imul")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
......@@ -489,7 +618,8 @@
(set (match_operand:SI 3 "gpc_reg_operand" "=q")
(mod:SI (match_dup 1) (match_dup 2)))]
""
"divs %0,%1,%2")
"divs %0,%1,%2"
[(set_attr "type" "idiv")])
;; For powers of two we can do srai/aze for divide and then adjust for
;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
......@@ -571,7 +701,8 @@
(match_dup 3)))]
""
"div %0,%1,%3")
"div %0,%1,%3"
[(set_attr "type" "idiv")])
;; To do unsigned divide we handle the cases of the divisor looking like a
;; negative number. If it is a constant that is less than 2**31, we don't
......@@ -1686,7 +1817,7 @@
(match_operand:SF 2 "gpc_reg_operand" "f")))]
""
"fd %0,%1,%2"
[(set_attr "type" "fp")])
[(set_attr "type" "sdiv")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
......@@ -1767,7 +1898,7 @@
(match_operand:DF 2 "gpc_reg_operand" "f")))]
""
"fm %0,%1,%2"
[(set_attr "type" "fp")])
[(set_attr "type" "dmul")])
(define_insn "divdf3"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
......@@ -1775,7 +1906,7 @@
(match_operand:DF 2 "gpc_reg_operand" "f")))]
""
"fd %0,%1,%2"
[(set_attr "type" "fp")])
[(set_attr "type" "ddiv")])
(define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
......@@ -1784,7 +1915,7 @@
(match_operand:DF 3 "gpc_reg_operand" "f")))]
""
"fma %0,%1,%2,%3"
[(set_attr "type" "fp")])
[(set_attr "type" "dmul")])
(define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
......@@ -1793,7 +1924,7 @@
(match_operand:DF 3 "gpc_reg_operand" "f")))]
""
"fms %0,%1,%2,%3"
[(set_attr "type" "fp")])
[(set_attr "type" "dmul")])
(define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
......@@ -1802,7 +1933,7 @@
(match_operand:DF 3 "gpc_reg_operand" "f"))))]
""
"fnma %0,%1,%2,%3"
[(set_attr "type" "fp")])
[(set_attr "type" "dmul")])
(define_insn ""
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
......@@ -1811,7 +1942,7 @@
(match_operand:DF 3 "gpc_reg_operand" "f"))))]
""
"fnms %0,%1,%2,%3"
[(set_attr "type" "fp")])
[(set_attr "type" "dmul")])
;; Conversions to and from floating-point.
(define_expand "floatsidf2"
......@@ -2367,7 +2498,7 @@
fmr %0,%1
lfs%U1%X1 %0,%1
frsp %1,%1\;stfs%U0%X0 %1,%0"
[(set_attr "type" "fp,load,*")
[(set_attr "type" "fp,fpload,*")
(set_attr "length" "*,*,8")])
(define_expand "movdf"
......@@ -2728,7 +2859,7 @@
"@
lux %3,%0,%2
lu %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "load")])
(define_insn ""
[(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
......@@ -2751,7 +2882,7 @@
"@
lhzux %3,%0,%2
lhzu %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "load")])
(define_insn ""
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
......@@ -2764,7 +2895,7 @@
"@
lhzux %3,%0,%2
lhzu %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "load")])
(define_insn ""
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
......@@ -2777,7 +2908,7 @@
"@
lhaux %3,%0,%2
lhau %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "load")])
(define_insn ""
[(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
......@@ -2788,8 +2919,7 @@
""
"@
sthux %3,%0,%2
sthu %3,%2(%0)"
[(set_attr "type" "load,load")])
sthu %3,%2(%0)")
(define_insn ""
[(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
......@@ -2801,7 +2931,7 @@
"@
lbzux %3,%0,%2
lbzu %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "load")])
(define_insn ""
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
......@@ -2814,7 +2944,7 @@
"@
lbzux %3,%0,%2
lbzu %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "load")])
(define_insn ""
[(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
......@@ -2837,7 +2967,7 @@
"@
lfsux %3,%0,%2
lfsu %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "fpload")])
(define_insn ""
[(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
......@@ -2860,7 +2990,7 @@
"@
lfdux %3,%0,%2
lfdu %3,%2(%0)"
[(set_attr "type" "load,load")])
[(set_attr "type" "fpload")])
(define_insn ""
[(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
......
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