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Commit cfa55545 by Bilyan Borisov Committed by James Greenhalgh
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[AARCH64][PATCH 3/3] Adding tests to check proper error reporting of out of... 

[AARCH64][PATCH 3/3] Adding tests to check proper error reporting of out
of bounds accesses to vmulx_lane* NEON intrinsics

gcc/testsuite/

	* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c:
	New.

From-SVN: r230800
parent 895548a5
Showing with 219 additions and 0 deletions
gcc/testsuite/ChangeLog
2015-11-24 Bilyan Borisov <bilyan.borisov@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c:
New.
* gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c:
New.
2015-11-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR middle-end/68375
......
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float32x2_t
f_vmulx_lane_f32 (float32x2_t v1, float32x2_t v2)
{
float32x2_t res;
/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vmulx_lane_f32 (v1, v2, -1);
/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vmulx_lane_f32 (v1, v2, 2);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1_t
f_vmulx_lane_f64 (float64x1_t v1, float64x1_t v2)
{
float64x1_t res;
/* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vmulx_lane_f64 (v1, v2, -1);
/* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vmulx_lane_f64 (v1, v2, 1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float32x2_t
f_vmulx_laneq_f32 (float32x2_t v1, float32x4_t v2)
{
float32x2_t res;
/* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
res = vmulx_laneq_f32 (v1, v2, -1);
/* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
res = vmulx_laneq_f32 (v1, v2, 4);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1_t
f_vmulx_laneq_f64 (float64x1_t v1, float64x2_t v2)
{
float64x1_t res;
/* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulx_laneq_f64 (v1, v2, -1);
/* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulx_laneq_f64 (v1, v2, 2);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64_t
f_vmulxd_lane_f64 (float64_t v1, float64x1_t v2)
{
float64_t res;
/* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */
res = vmulxd_lane_f64 (v1, v2, -1);
/* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */
res = vmulxd_lane_f64 (v1, v2, 1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64_t
f_vmulxd_laneq_f64 (float64_t v1, float64x2_t v2)
{
float64_t res;
/* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulxd_laneq_f64 (v1, v2, -1);
/* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulxd_laneq_f64 (v1, v2, 2);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float32x4_t
f_vmulxq_lane_f32 (float32x4_t v1, float32x2_t v2)
{
float32x4_t res;
/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vmulxq_lane_f32 (v1, v2, -1);
/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vmulxq_lane_f32 (v1, v2, 2);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2_t
f_vmulxq_lane_f64 (float64x2_t v1, float64x1_t v2)
{
float64x2_t res;
/* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */
res = vmulxq_lane_f64 (v1, v2, -1);
/* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */
res = vmulxq_lane_f64 (v1, v2, 1);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float32x4_t
f_vmulxq_laneq_f32 (float32x4_t v1, float32x4_t v2)
{
float32x4_t res;
/* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
res = vmulxq_laneq_f32 (v1, v2, -1);
/* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
res = vmulxq_laneq_f32 (v1, v2, 4);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2_t
f_vmulxq_laneq_f64 (float64x2_t v1, float64x2_t v2)
{
float64x2_t res;
/* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulxq_laneq_f64 (v1, v2, -1);
/* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulxq_laneq_f64 (v1, v2, 2);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float32_t
f_vmulxs_lane_f32 (float32_t v1, float32x2_t v2)
{
float32_t res;
/* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulxs_lane_f32 (v1, v2, -1);
/* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
res = vmulxs_lane_f32 (v1, v2, 2);
return res;
}
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c 0 → 100644
#include <arm_neon.h>
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
/* { dg-skip-if "" { arm*-*-* } } */
float32_t
f_vmulxs_laneq_f32 (float32_t v1, float32x4_t v2)
{
float32_t res;
/* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
res = vmulxs_laneq_f32 (v1, v2, -1);
/* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
res = vmulxs_laneq_f32 (v1, v2, 4);
return res;
}
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