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Commit ce9dbf20 by Claudiu Zissulescu Committed by Claudiu Zissulescu
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[ARC] Fix and refurbish the interrupts. 

When entering an interrupt, not only the call save registers needs to
be place on stack but also the call clobbers one. More over, the
ARC700 return from interrupt instruction needs to be rtie, the same
like ARCv2 CPUs. While the ARC6xx family uses j.f [ilinkX]
instruction. Additionally, we need to save the state of the ZOL
machinery, namely the lp_count, lp_end and lp_start registers. For
architectures which are using extension registers (i.e., HS48) we need
to save/restore them as well.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-protos.h (arc_output_function_epilogue): Delete
	declaration.
	(arc_compute_frame_size): Millicode is disabled when compiling
	ISR.
	(arc_return_address_register): Likewise.
	(arc_compute_function_type): Likewise.
	(arc_compute_frame_size): Likewise.
	(secondary_reload_info): Likewise.
	(arc_get_unalign): Likewise.
	(arc_can_use_return_insn): Declare.
	* config/arc/arc.c (AUX_LP_START): Define
	(AUX_LP_END): Likewise.
	(arc_frame_info): Update gmask member to 64-bit datum.
	(GMASK_LEN): Update.
	(arc_compute_function_type): Make it static, move it forward.
	(arc_must_save_register): Update, consider the extra regs.
	(arc_compute_millicode_save_restore_regs): Update to use the 64
	bit gmask.
	(arc_compute_frame_size): Likewise.
	(arc_enter_leave_p): Likewise.
	(arc_save_callee_saves): Likewise.
	(arc_restore_callee_saves): Likewise.
	(arc_save_callee_enter): Likewise.
	(arc_restore_callee_leave): Likewise.
	(arc_save_callee_milli): Likewise.
	(arc_restore_callee_milli): Likewise.
	(arc_expand_prologue): Add new interrupt handling.
	(arc_return_address_register): Make it static, move it forward.
	(arc_expand_epilogue): Add new interrupt handling.
	(arc_get_unalign): Delete.
	(arc_epilogue_uses): Make sure we do not remove the extra
	saved/restored registers when interrupt.
	(arc_can_use_return_insn): New function.
	(push_reg): Likewise.
	(pop_reg): Likewise.
	(arc_save_callee_saves): Add ZOL and FPX aux registers saving
	procedures.
	(arc_restore_callee_saves): Likewise, but restoring.
	* config/arc/arc.md (VUNSPEC_ARC_ARC600_RTIE): Define.
	(R33_REG): Likewise.
	(R34_REG): Likewise.
	(R35_REG): Likewise.
	(R36_REG): Likewise.
	(R37_REG): Likewise.
	(R38_REG): Likewise.
	(R39_REG): Likewise.
	(R45_REG): Likewise.
	(R46_REG): Likewise.
	(R47_REG): Likewise.
	(R48_REG): Likewise.
	(R49_REG): Likewise.
	(R50_REG): Likewise.
	(R51_REG): Likewise.
	(R52_REG): Likewise.
	(R53_REG): Likewise.
	(R54_REG): Likewise.
	(R55_REG): Likewise.
	(R56_REG): Likewise.
	(R58_REG): Likewise.
	(type): Add rtie attribute.
	(in_call_delay_slot): Use RETURN_ADDR_REGNUM.
	(movsi_insn): Accept moves to lp_count.
	(rtie): Update pattern.
	(simple_return): Simplify it, don't use this pattern as a return
	from an interrupt.
	(arc600_rtie): New pattern.
	(p_return_i): Clean up.
	(return): Likewise.
	* config/arc/builtins.def (rtie): Only available for non ARC6xx
	family CPUs.
	* config/arc/predicates.md (move_src_operand): Consider lp_count
	as a register.

gcc/testsuite
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/arc.exp (check_effective_target_accregs): New
	predicate.
	* gcc.target/arc/builtin_special.c: Update test/
	* gcc.target/arc/interrupt-1.c: Likewise.
	* gcc.target/arc/interrupt-10.c: New test.
	* gcc.target/arc/interrupt-11.c: Likewise.
	* gcc.target/arc/interrupt-12.c: Likewise.

update

From-SVN: r273761
parent 4caa6bab
Showing with 240 additions and 87 deletions
gcc/ChangeLog
2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (arc_output_function_epilogue): Delete
declaration.
(arc_compute_frame_size): Millicode is disabled when compiling
ISR.
(arc_return_address_register): Likewise.
(arc_compute_function_type): Likewise.
(arc_compute_frame_size): Likewise.
(secondary_reload_info): Likewise.
(arc_get_unalign): Likewise.
(arc_can_use_return_insn): Declare.
* config/arc/arc.c (AUX_LP_START): Define
(AUX_LP_END): Likewise.
(arc_frame_info): Update gmask member to 64-bit datum.
(GMASK_LEN): Update.
(arc_compute_function_type): Make it static, move it forward.
(arc_must_save_register): Update, consider the extra regs.
(arc_compute_millicode_save_restore_regs): Update to use the 64
bit gmask.
(arc_compute_frame_size): Likewise.
(arc_enter_leave_p): Likewise.
(arc_save_callee_saves): Likewise.
(arc_restore_callee_saves): Likewise.
(arc_save_callee_enter): Likewise.
(arc_restore_callee_leave): Likewise.
(arc_save_callee_milli): Likewise.
(arc_restore_callee_milli): Likewise.
(arc_expand_prologue): Add new interrupt handling.
(arc_return_address_register): Make it static, move it forward.
(arc_expand_epilogue): Add new interrupt handling.
(arc_get_unalign): Delete.
(arc_epilogue_uses): Make sure we do not remove the extra
saved/restored registers when interrupt.
(arc_can_use_return_insn): New function.
(push_reg): Likewise.
(pop_reg): Likewise.
(arc_save_callee_saves): Add ZOL and FPX aux registers saving
procedures.
(arc_restore_callee_saves): Likewise, but restoring.
* config/arc/arc.md (VUNSPEC_ARC_ARC600_RTIE): Define.
(R33_REG): Likewise.
(R34_REG): Likewise.
(R35_REG): Likewise.
(R36_REG): Likewise.
(R37_REG): Likewise.
(R38_REG): Likewise.
(R39_REG): Likewise.
(R45_REG): Likewise.
(R46_REG): Likewise.
(R47_REG): Likewise.
(R48_REG): Likewise.
(R49_REG): Likewise.
(R50_REG): Likewise.
(R51_REG): Likewise.
(R52_REG): Likewise.
(R53_REG): Likewise.
(R54_REG): Likewise.
(R55_REG): Likewise.
(R56_REG): Likewise.
(R58_REG): Likewise.
(type): Add rtie attribute.
(in_call_delay_slot): Use RETURN_ADDR_REGNUM.
(movsi_insn): Accept moves to lp_count.
(rtie): Update pattern.
(simple_return): Simplify it, don't use this pattern as a return
from an interrupt.
(arc600_rtie): New pattern.
(p_return_i): Clean up.
(return): Likewise.
* config/arc/builtins.def (rtie): Only available for non ARC6xx
family CPUs.
* config/arc/predicates.md (move_src_operand): Consider lp_count
as a register.
2019-07-24 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/predicates.md (addv_const_operand): New predicate.
......
gcc/config/arc/arc-protos.h
......@@ -25,7 +25,6 @@ extern machine_mode arc_select_cc_mode (enum rtx_code, rtx, rtx);
extern struct rtx_def *gen_compare_reg (rtx, machine_mode);
/* Declarations for various fns used in the .md file. */
extern void arc_output_function_epilogue (FILE *, HOST_WIDE_INT, int);
extern const char *output_shift (rtx *);
extern bool compact_sda_memory_operand (rtx, machine_mode, bool);
extern bool arc_double_limm_p (rtx);
......@@ -42,8 +41,6 @@ extern void arc_expand_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
extern void arc_split_compare_and_swap (rtx *);
extern void arc_expand_compare_and_swap (rtx *);
extern bool compact_memory_operand_p (rtx, machine_mode, bool, bool);
extern int arc_return_address_register (unsigned int);
extern unsigned int arc_compute_function_type (struct function *);
extern bool arc_is_uncached_mem_p (rtx);
extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute);
extern bool arc_check_multi (rtx, bool);
......@@ -52,9 +49,9 @@ extern bool arc_check_ior_const (HOST_WIDE_INT );
extern void arc_split_ior (rtx *);
extern bool arc_check_mov_const (HOST_WIDE_INT );
extern bool arc_split_mov_const (rtx *);
extern bool arc_can_use_return_insn (void);
#endif /* RTX_CODE */
extern unsigned int arc_compute_frame_size (int);
extern bool arc_ccfsm_branch_deleted_p (void);
extern void arc_ccfsm_record_branch_deleted (void);
......@@ -71,7 +68,6 @@ extern bool arc_is_longcall_p (rtx);
extern bool arc_is_shortcall_p (rtx);
extern bool valid_brcc_with_delay_p (rtx *);
extern bool arc_ccfsm_cond_exec_p (void);
struct secondary_reload_info;
extern rtx disi_highpart (rtx);
extern int arc_adjust_insn_length (rtx_insn *, int, bool);
extern int arc_corereg_hazard (rtx, rtx);
......@@ -89,7 +85,6 @@ extern void arc_expand_prologue (void);
extern void arc_expand_epilogue (int);
extern void arc_init_expanders (void);
extern int arc_check_millicode (rtx op, int offset, int load_p);
extern int arc_get_unalign (void);
extern void arc_clear_unalign (void);
extern void arc_toggle_unalign (void);
extern void split_addsi (rtx *);
......
gcc/config/arc/arc.md
......@@ -163,6 +163,7 @@
VUNSPEC_ARC_LL
VUNSPEC_ARC_BLOCKAGE
VUNSPEC_ARC_EH_RETURN
VUNSPEC_ARC_ARC600_RTIE
])
(define_constants
......@@ -187,17 +188,37 @@
(R30_REG 30)
(RETURN_ADDR_REGNUM 31)
(R32_REG 32)
(R33_REG 33)
(R34_REG 34)
(R35_REG 35)
(R36_REG 36)
(R37_REG 37)
(R38_REG 38)
(R39_REG 39)
(R40_REG 40)
(R41_REG 41)
(R42_REG 42)
(R43_REG 43)
(R44_REG 44)
(R45_REG 45)
(R46_REG 46)
(R47_REG 47)
(R48_REG 48)
(R49_REG 49)
(R50_REG 50)
(R51_REG 51)
(R52_REG 52)
(R53_REG 53)
(R54_REG 54)
(R55_REG 55)
(R56_REG 56)
(R57_REG 57)
(R58_REG 58)
(R59_REG 59)
(MUL64_OUT_REG 58)
(MUL32x16_REG 56)
(ARCV2_ACC 58)
(R59_REG 59)
(LP_COUNT 60)
(CC_REG 61)
(PCL_REG 63)
......@@ -214,7 +235,7 @@
(define_attr "type"
"move,load,store,cmove,unary,binary,compare,shift,uncond_branch,jump,branch,
brcc,brcc_no_delay_slot,call,sfunc,call_no_delay_slot,
brcc,brcc_no_delay_slot,call,sfunc,call_no_delay_slot,rtie,
multi,umulti, two_cycle_core,lr,sr,divaw,loop_setup,loop_end,return,
misc,spfp,dpfp_mult,dpfp_addsub,mulmac_600,cc_arith,
simd_vload, simd_vload128, simd_vstore, simd_vmove, simd_vmove_else_zero,
......@@ -531,9 +552,7 @@
(cond [(eq_attr "in_delay_slot" "false")
(const_string "no")
(match_test "regno_clobbered_p
(arc_return_address_register
(arc_compute_function_type (cfun)),
insn, SImode, 1)")
(RETURN_ADDR_REGNUM, insn, SImode, 1)")
(const_string "no")]
(const_string "yes")))
......@@ -757,9 +776,9 @@ core_3, archs4x, archs4xd, archs4xd_slow"
; execution must reflect this, lest out-of-range branches are created.
; the iscompact attribute allows the epilogue expander to know for which
; insns it should lengthen the return insn.
(define_insn_and_split "*movsi_insn" ; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
[(set (match_operand:SI 0 "move_dest_operand" "=q, q,r,q, h,rl, r, r, r, r, ?r, r, q, h, rl, q, S, Us<,RcqRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m, m,VUsc")
(match_operand:SI 1 "move_src_operand" "rL,rP,q,P,hCm1,rL, I,Clo,Chi,Cbi,Cpc,Clb,Cax,Cal,Cal,Uts,Rcq,RcqRck, Us>,Usd,Ucm, Usd, Ucd,m, r,!*Rzd,r,Cm3, C32"))]
(define_insn_and_split "*movsi_insn" ; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
[(set (match_operand:SI 0 "move_dest_operand" "=q, q,r,q, h, rl,r, r, r, r, ?r, r, q, h, rl, q, S, Us<,RcqRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m, m,VUsc")
(match_operand:SI 1 "move_src_operand" "rL,rP,q,P,hCm1,rLl,I,Clo,Chi,Cbi,Cpc,Clb,Cax,Cal,Cal,Uts,Rcq,RcqRck, Us>,Usd,Ucm, Usd, Ucd,m, r,!*Rzd,r,Cm3, C32"))]
"register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)
|| (CONSTANT_P (operands[1])
......@@ -775,8 +794,8 @@ core_3, archs4x, archs4xd, archs4xd_slow"
mov%?\\t%0,%1 ;4
mov%?\\t%0,%1 ;5
mov%?\\t%0,%1 ;6
movl.cl\\t %0,%1 ;7
movh.cl\\t %0,%L1>>16 ;8
movl.cl\\t%0,%1 ;7
movh.cl\\t%0,%L1>>16 ;8
* return INTVAL (operands[1]) & 0xffffff ? \"movbi.cl\\t%0,%1 >> %p1,%p1,8;9\" : \"movbi.cl\\t%0,%L1 >> 24,24,8;9\";
add\\t%0,%1 ;10
add\\t%0,pcl,%1@pcl ;11
......@@ -784,7 +803,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
mov%?\\t%0,%j1 ;13
mov%?\\t%0,%j1 ;14
ld%?\\t%0,%1 ;15
st%?\\t %1,%0 ;16
st%?\\t%1,%0 ;16
* return arc_short_long (insn, \"push%?\\t%1%&\", \"st%U0\\t%1,%0%&\");
* return arc_short_long (insn, \"pop%?\\t%0%&\", \"ld%U1\\t%0,%1%&\");
ld%?\\t%0,%1 ;19
......@@ -4560,13 +4579,13 @@ core_3, archs4x, archs4xd, archs4xd_slow"
(set_attr "type" "misc")])
(define_insn "rtie"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")]
VUNSPEC_ARC_RTIE)]
""
[(return)
(unspec_volatile [(const_int 0)] VUNSPEC_ARC_RTIE)]
"!TARGET_ARC600_FAMILY"
"rtie"
[(set_attr "length" "4")
(set_attr "type" "misc")
(set_attr "cond" "clob")])
(set_attr "type" "rtie")
(set_attr "cond" "clob")])
(define_insn "sync"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")]
......@@ -4788,88 +4807,52 @@ core_3, archs4x, archs4xd, archs4xd_slow"
; forbid instructions that change blink in the return / sibcall delay slot.
(define_insn "simple_return"
[(simple_return)]
"reload_completed"
{
rtx reg
= gen_rtx_REG (Pmode,
arc_return_address_register (arc_compute_function_type
(cfun)));
""
"j%!%*\\t[blink]"
[(set_attr "type" "return")
(set_attr "cond" "canuse")
(set_attr "iscompact" "maybe")
(set_attr "length" "*")])
if (TARGET_V2
&& ARC_INTERRUPT_P (arc_compute_function_type (cfun)))
{
return \"rtie\";
}
output_asm_insn (\"j%!%* [%0]%&\", &reg);
return \"\";
}
[(set (attr "type")
(cond [(and (match_test "ARC_INTERRUPT_P (arc_compute_function_type (cfun))")
(match_test "TARGET_V2"))
(const_string "brcc_no_delay_slot")]
(const_string "return")))
; predicable won't help here since the canonical rtl looks different
; for branches.
(set (attr "cond")
(cond [(and (eq (symbol_ref "arc_compute_function_type (cfun)")
(symbol_ref "ARC_FUNCTION_ILINK1"))
(match_test "TARGET_V2"))
(const_string "nocond")]
(const_string "canuse")))
(set (attr "iscompact")
(cond [(eq (symbol_ref "arc_compute_function_type (cfun)")
(symbol_ref "ARC_FUNCTION_NORMAL"))
(const_string "maybe")]
(const_string "false")))
(set (attr "length")
(cond [(ne (symbol_ref "arc_compute_function_type (cfun)")
(symbol_ref "ARC_FUNCTION_NORMAL"))
(const_int 4)]
(const_int 2)))])
(define_insn "arc600_rtie"
[(return)
(unspec_volatile [(match_operand 0 "pmode_register_operand" "")]
VUNSPEC_ARC_ARC600_RTIE)]
"TARGET_ARC600_FAMILY"
"j.f\\t[%0]"
[(set_attr "length" "4")
(set_attr "type" "rtie")
(set_attr "cond" "clob")])
(define_insn "p_return_i"
[(set (pc)
(if_then_else (match_operator 0 "proper_comparison_operator"
[(reg CC_REG) (const_int 0)])
(simple_return) (pc)))]
"reload_completed
&& !(TARGET_V2
&& ARC_INTERRUPT_P (arc_compute_function_type (cfun)))"
"reload_completed"
{
rtx xop[2];
xop[0] = operands[0];
xop[1]
= gen_rtx_REG (Pmode,
arc_return_address_register (arc_compute_function_type
(cfun)));
output_asm_insn (\"j%d0%!%# [%1]%&\", xop);
output_asm_insn (\"j%d0%!%#\\t[blink]\", operands);
/* record the condition in case there is a delay insn. */
arc_ccfsm_record_condition (xop[0], false, insn, 0);
arc_ccfsm_record_condition (operands[0], false, insn, 0);
return \"\";
}
[(set_attr "type" "return")
(set_attr "cond" "use")
(set (attr "iscompact")
(cond [(eq (symbol_ref "arc_compute_function_type (cfun)")
(symbol_ref "ARC_FUNCTION_NORMAL"))
(const_string "maybe")]
(const_string "false")))
(set_attr "iscompact" "maybe" )
(set (attr "length")
(cond [(ne (symbol_ref "arc_compute_function_type (cfun)")
(symbol_ref "ARC_FUNCTION_NORMAL"))
(const_int 4)
(not (match_operand 0 "equality_comparison_operator" ""))
(cond [(not (match_operand 0 "equality_comparison_operator" ""))
(const_int 4)
(eq_attr "delay_slot_filled" "yes")
(const_int 4)]
(const_int 2)))])
;; ??? #ifdefs in function.c require the presence of this pattern, with a
;; non-constant predicate.
;; Return nonzero if this function is known to have a null epilogue.
;; This allows the optimizer to omit jumps to jumps if no stack
;; was created.
(define_expand "return"
[(return)]
"optimize < 0")
"arc_can_use_return_insn ()"
"")
;; Comment in final.c (insn_current_reference_address) says
;; forward branch addresses are calculated from the next insn after branch
......
gcc/config/arc/builtins.def
......@@ -33,7 +33,7 @@
/* Special builtins. */
DEF_BUILTIN (NOP, 0, void_ftype_void, nothing, 1)
DEF_BUILTIN (RTIE, 0, void_ftype_void, rtie, 1)
DEF_BUILTIN (RTIE, 0, void_ftype_void, rtie, !TARGET_ARC600_FAMILY)
DEF_BUILTIN (SYNC, 0, void_ftype_void, sync, 1)
DEF_BUILTIN (BRK, 0, void_ftype_void, brk, 1)
DEF_BUILTIN (SWI, 0, void_ftype_void, swi, 1)
......
gcc/config/arc/predicates.md
......@@ -285,6 +285,8 @@
return GET_MODE (op) == SFmode;
return 0;
case REG :
if (REGNO (op) == LP_COUNT)
return 1;
return register_operand (op, mode);
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
......
gcc/testsuite/ChangeLog
2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/arc.exp (check_effective_target_accregs): New
predicate.
* gcc.target/arc/builtin_special.c: Update test/
* gcc.target/arc/interrupt-1.c: Likewise.
* gcc.target/arc/interrupt-10.c: New test.
* gcc.target/arc/interrupt-11.c: Likewise.
* gcc.target/arc/interrupt-12.c: Likewise.
2019-07-24 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/addsub-signed-overflow-1.c: New test.
......
gcc/testsuite/gcc.target/arc/arc.exp
......@@ -94,6 +94,24 @@ proc check_effective_target_barrelshifter { } {
}]
}
#return 1 if we use ARCv2 Accumulator registers
proc check_effective_target_accregs { } {
return [check_no_compiler_messages accregs assembly {
#if !defined(__ARC_MPY_DMPY__) \
&& !defined(__ARC_MPY_MACD__) && !defined(__ARC_MPY_QMACW__)
#error No accumulator available for this config
#endif
}]
}
proc check_effective_target_dpfp { } {
return [check_no_compiler_messages dpfp assembly {
#if !defined(__ARC_FPX_DP__) && !defined(__ARC_FPU_ASSIST__)
#error No FPX available for this config
#endif
}]
}
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
......
gcc/testsuite/gcc.target/arc/builtin_special.c
......@@ -21,7 +21,9 @@
NORET (nop)
#if !defined (__ARC600__) && !defined (__ARC601__)
NORET (rtie)
#endif
#ifdef __A7__
NORET (sync)
......
gcc/testsuite/gcc.target/arc/interrupt-1.c
......@@ -6,5 +6,5 @@ void __attribute__ ((interrupt("ilink1")))
handler1 (void)
{
}
/* { dg-final { scan-assembler-times "j.*\[ilink1\]" 1 { target { arc700 || arc6xx } } } } */
/* { dg-final { scan-assembler-times "rtie" 1 { target { arcem || archs } } } } */
/* { dg-final { scan-assembler-times "j.*\[ilink1\]" 1 { target { arc6xx } } } } */
/* { dg-final { scan-assembler-times "rtie" 1 { target { ! { arc6xx } } } } } */
gcc/testsuite/gcc.target/arc/interrupt-10.c 0 → 100644
/* { dg-options "-O2" } */
extern void will_trig_exception(void);
#if defined (__ARCHS__) || defined (__ARCEM__)
__attribute__ ((interrupt("ilink")))
#else
__attribute__ ((interrupt("ilink1")))
#endif
void isr_0 (void)
{
will_trig_exception();
}
/* { dg-final { scan-assembler-times "j.*\[ilink1\]" 1 { target { arc6xx } } } } */
/* { dg-final { scan-assembler-times "rtie" 1 { target { ! { arc6xx } } } } } */
/* { dg-final { scan-assembler-times "blink" 2 } } */
/* { dg-final { scan-assembler-times "fp" 2 { target { ! { archs } } } } } */
/* { dg-final { scan-assembler-times "r30" 2 { target { archs || arcem } } } } */
/* { dg-final { scan-assembler-times "r24" 2 } } */
/* { dg-final { scan-assembler-times "r22" 2 } } */
/* { dg-final { scan-assembler-times "r20" 2 } } */
/* { dg-final { scan-assembler-times "r18" 2 } } */
/* { dg-final { scan-assembler-times "r16" 2 } } */
/* { dg-final { scan-assembler-times "r14" 2 } } */
/* { dg-final { scan-assembler-times "r12" 2 } } */
/* { dg-final { scan-assembler-times "r10" 2 } } */
/* { dg-final { scan-assembler-times "r8" 2 } } */
/* { dg-final { scan-assembler-times "r6" 2 } } */
/* { dg-final { scan-assembler-times "r4" 2 } } */
/* { dg-final { scan-assembler-times "r2\[,\n\]" 2 } } */
/* { dg-final { scan-assembler-times "lp_count" 2 } } */
/* { dg-final { scan-assembler-times "sr\\s+r\[0-9\]," 2 { target { ! { dpfp } } } } } */
/* { dg-final { scan-assembler-times "lr\\s+r\[0-9\]" 2 { target { ! { dpfp } } } } } */
/* { dg-final { scan-assembler-times "sr\\s+r\[0-9\]," 6 { target { dpfp } } } } */
/* { dg-final { scan-assembler-times "lr\\s+r\[0-9\]" 6 { target { dpfp } } } } */
/* { dg-final { scan-assembler-times "r58" 2 { target { accregs } } } } */
gcc/testsuite/gcc.target/arc/interrupt-11.c 0 → 100644
extern int a;
#if defined (__ARCHS__) || defined (__ARCEM__)
__attribute__ ((interrupt("ilink")))
#else
__attribute__ ((interrupt("ilink2")))
#endif
void isr_1 (void)
{
a++;
}
/* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 { target { arc6xx } } } } */
/* { dg-final { scan-assembler-times "rtie" 1 { target { ! { arc6xx } } } } } */
/* { dg-final { scan-assembler-times "push_s\\s+r\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "pop_s\\s+r\[0-9\]" 1 } } */
gcc/testsuite/gcc.target/arc/interrupt-12.c 0 → 100644
/* { dg-options "-O0 -g" } */
typedef void (*isr_routine)(void);
isr_routine will_trig_exception;
#if defined (__ARCHS__) || defined (__ARCEM__)
void __attribute__ ((interrupt("ilink")))
#else
void __attribute__ ((interrupt("ilink1")))
#endif
isr_template(void)
{
will_trig_exception();
}
/* { dg-final { scan-assembler-times "\\\.cfi_offset 0" 1 } } */
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