re PR target/84845 (ICE: in extract_insn, at recog.c:2304: unrecognizable insn…

re PR target/84845 (ICE: in extract_insn, at recog.c:2304: unrecognizable insn at -O2 and above at aarch64)

	PR target/84845
	* config/aarch64/aarch64.md (*aarch64_reg_<mode>3_neg_mask2): Rename
	to ...
	(*aarch64_<optab>_reg_<mode>3_neg_mask2): ... this.  If pseudos can't
	be created, use lowpart_subreg of operands[0] rather than operands[0]
	itself.
	(*aarch64_reg_<mode>3_minus_mask): Rename to ...
	(*aarch64_ashl_reg_<mode>3_minus_mask): ... this.
	(*aarch64_<optab>_reg_di3_mask2): Use const_int_operand predicate
	and n constraint instead of aarch64_shift_imm_di and Usd.
	(*aarch64_reg_<optab>_minus<mode>3): Rename to ...
	(*aarch64_<optab>_reg_minus<mode>3): ... this.

	* gcc.c-torture/compile/pr84845.c: New test.

From-SVN: r258678

gcc/ChangeLog

+2018-03-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/84845
+	* config/aarch64/aarch64.md (*aarch64_reg_<mode>3_neg_mask2): Rename
+	to ...
+	(*aarch64_<optab>_reg_<mode>3_neg_mask2): ... this.  If pseudos can't
+	be created, use lowpart_subreg of operands[0] rather than operands[0]
+	itself.
+	(*aarch64_reg_<mode>3_minus_mask): Rename to ...
+	(*aarch64_ashl_reg_<mode>3_minus_mask): ... this.
+	(*aarch64_<optab>_reg_di3_mask2): Use const_int_operand predicate
+	and n constraint instead of aarch64_shift_imm_di and Usd.
+	(*aarch64_reg_<optab>_minus<mode>3): Rename to ...
+	(*aarch64_<optab>_reg_minus<mode>3): ... this.
+
 2018-03-20  Sudakshina Das  <sudi.das@arm.com>
 
 	PR target/82989

gcc/config/aarch64/aarch64.md

@@ -4282,7 +4282,7 @@
   [(set_attr "type" "shift_reg")]
 )
 
-(define_insn_and_split "*aarch64_reg_<mode>3_neg_mask2"
+(define_insn_and_split "*aarch64_<optab>_reg_<mode>3_neg_mask2"
   [(set (match_operand:GPI 0 "register_operand" "=&r")
 	(SHIFT:GPI
 	  (match_operand:GPI 1 "register_operand" "r")
@@ -4295,7 +4295,7 @@
   [(const_int 0)]
   {
     rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
-	       : operands[0]);
+	       : lowpart_subreg (SImode, operands[0], <MODE>mode));
     emit_insn (gen_negsi2 (tmp, operands[2]));
 
     rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
@@ -4306,7 +4306,7 @@
   }
 )
 
-(define_insn_and_split "*aarch64_reg_<mode>3_minus_mask"
+(define_insn_and_split "*aarch64_ashl_reg_<mode>3_minus_mask"
   [(set (match_operand:GPI 0 "register_operand" "=&r")
 	(ashift:GPI
 	  (match_operand:GPI 1 "register_operand" "r")
@@ -4340,8 +4340,8 @@
 	  (match_operand:DI 1 "register_operand" "r")
 	  (match_operator 4 "subreg_lowpart_operator"
 	   [(and:SI (match_operand:SI 2 "register_operand" "r")
-		     (match_operand 3 "aarch64_shift_imm_di" "Usd"))])))]
-  "((~INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1)) == 0)"
+		    (match_operand 3 "const_int_operand" "n"))])))]
+  "((~INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode) - 1)) == 0)"
 {
   rtx xop[3];
   xop[0] = operands[0];
@@ -4353,7 +4353,7 @@
   [(set_attr "type" "shift_reg")]
 )
 
-(define_insn_and_split "*aarch64_reg_<optab>_minus<mode>3"
+(define_insn_and_split "*aarch64_<optab>_reg_minus<mode>3"
   [(set (match_operand:GPI 0 "register_operand" "=&r")
 	(ASHIFT:GPI
 	  (match_operand:GPI 1 "register_operand" "r")

gcc/testsuite/ChangeLog

+2018-03-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/84845
+	* gcc.c-torture/compile/pr84845.c: New test.
+
 2018-03-20  Sudakshina Das  <sudi.das@arm.com>
 
 	PR target/82989

gcc/testsuite/gcc.c-torture/compile/pr84845.c

+/* PR target/84845 */
+
+int a, b, c;
+unsigned long d;
+
+void
+foo (void)
+{
+  b = -1;
+  b <<= c >= 0;
+  d = d << (63 & (short)-b) | d >> (63 & -(short)-b);
+}