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riscv-gcc-1
Commit cde21847 by Stan Cox Committed by Jeff Law
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i386.md: (movsicc_1, movhicc_1): For alternate 3 set the opcode suffix from operand 3. 

        * i386.md: (movsicc_1, movhicc_1):  For alternate 3 set the opcode
        suffix from operand 3.

From-SVN: r17317
parent 184bb750
Showing with 10 additions and 5 deletions
gcc/ChangeLog
Sat Jan 10 22:04:15 1998 Stan Cox <scox@equinox.cygnus.com>
* i386.md: (movsicc_1, movhicc_1): For alternate 3 set the opcode
suffix from operand 3.
Sat Jan 10 21:50:16 1998 J"orn Rennecke <amylaar@cygnus.co.uk>
Jeffrey A Law (law@cygnus.com)
......
gcc/config/i386/i386.md
; GCC machine description for Intel X86.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
;; Copyright (C) 1988, 94-97, 1998 Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; This file is part of GNU CC.
......@@ -7327,8 +7327,8 @@ byte_xor_operation:
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[3]) == MEM)
{
output_asm_insn (AS2 (mov%z2,%3,%4), operands);
output_asm_insn (AS2 (mov%z2,%4,%0), operands);
output_asm_insn (AS2 (mov%z3,%3,%4), operands);
output_asm_insn (AS2 (mov%z3,%4,%0), operands);
}
else
output_asm_insn (AS2 (mov%z0,%3,%0), operands);
......@@ -7388,8 +7388,8 @@ byte_xor_operation:
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[3]) == MEM)
{
output_asm_insn (AS2 (mov%z2,%3,%4), operands);
output_asm_insn (AS2 (mov%z2,%4,%0), operands);
output_asm_insn (AS2 (mov%z3,%3,%4), operands);
output_asm_insn (AS2 (mov%z3,%4,%0), operands);
}
else
output_asm_insn (AS2 (mov%z0,%3,%0), operands);
......
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