Commit cd9346a1 by Segher Boessenkool Committed by Segher Boessenkool

rs6000: Simplify <VSa> for VSX_TI

When used in VSX_TI, <VSa> is always just "wa".


	* config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_TI
	with just "wa".

From-SVN: r271933
parent 72e3386e
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_TI
with just "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "ww"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
......
......@@ -972,9 +972,9 @@
;; special V1TI container class, which it is not appropriate to use vec_select
;; for the type.
(define_insn "*vsx_le_permute_<mode>"
[(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=<VSa>,<VSa>,Z,&r,&r,Q")
[(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=wa,wa,Z,&r,&r,Q")
(rotate:VSX_TI
(match_operand:VSX_TI 1 "input_operand" "<VSa>,Z,<VSa>,r,Q,r")
(match_operand:VSX_TI 1 "input_operand" "wa,Z,wa,r,Q,r")
(const_int 64)))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"@
......@@ -988,10 +988,10 @@
(set_attr "type" "vecperm,vecload,vecstore,*,load,store")])
(define_insn_and_split "*vsx_le_undo_permute_<mode>"
[(set (match_operand:VSX_TI 0 "vsx_register_operand" "=<VSa>,<VSa>")
[(set (match_operand:VSX_TI 0 "vsx_register_operand" "=wa,wa")
(rotate:VSX_TI
(rotate:VSX_TI
(match_operand:VSX_TI 1 "vsx_register_operand" "0,<VSa>")
(match_operand:VSX_TI 1 "vsx_register_operand" "0,wa")
(const_int 64))
(const_int 64)))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
......
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