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Commit cd17b213 by Steve Ellcey Committed by Steve Ellcey
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re PR target/41365 (gcc.dg/vect/vect-cond-[123].c abort due to bad code… 

re PR target/41365 (gcc.dg/vect/vect-cond-[123].c abort due to bad code generation at -O1 and above)

2009-09-29  Steve Ellcey  <sje@cup.hp.com>
	    Alexander Monakov  <amonakov@ispras.ru>

	PR target/41365 
	* config/ia64/predicates.md (not_postinc_destination_operand): New.
	(not_postinc_memory_operand): New.
	(not_postinc_move_operand): New.
	* config/ia64/ia64.md (*cmovdi_internal): Disallow autoincrement.
	(*cmovsi_internal): Ditto.

Co-Authored-By: Alexander Monakov <amonakov@ispras.ru>

From-SVN: r152306
parent e7ada00d
Showing with 32 additions and 9 deletions
gcc/ChangeLog
2009-09-29 Steve Ellcey <sje@cup.hp.com>
Alexander Monakov <amonakov@ispras.ru>
PR target/41365
* config/ia64/predicates.md (not_postinc_destination_operand): New.
(not_postinc_memory_operand): New.
(not_postinc_move_operand): New.
* config/ia64/ia64.md (*cmovdi_internal): Disallow autoincrement.
(*cmovsi_internal): Ditto.
2009-09-29 Pat Haugen <pthaugen@us.ibm.com> 2009-09-29 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/rs6000.c (rs6000_issue_rate): Don't artificially * config/rs6000/rs6000.c (rs6000_issue_rate): Don't artificially
gcc/config/ia64/ia64.md
...@@ -4083,16 +4083,16 @@ ...@@ -4083,16 +4083,16 @@
;; ;;
(define_insn "*cmovdi_internal" (define_insn "*cmovdi_internal"
[(set (match_operand:DI 0 "destination_operand" [(set (match_operand:DI 0 "not_postinc_destination_operand"
"= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
(if_then_else:DI (if_then_else:DI
(match_operator 4 "predicate_operator" (match_operator 4 "predicate_operator"
[(match_operand:BI 1 "register_operand" [(match_operand:BI 1 "register_operand"
"c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
(const_int 0)]) (const_int 0)])
(match_operand:DI 2 "move_operand" (match_operand:DI 2 "not_postinc_move_operand"
"rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
(match_operand:DI 3 "move_operand" (match_operand:DI 3 "not_postinc_move_operand"
"rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
"ia64_move_ok (operands[0], operands[2]) "ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])" && ia64_move_ok (operands[0], operands[3])"
...@@ -4100,13 +4100,13 @@ ...@@ -4100,13 +4100,13 @@
[(set_attr "predicable" "no")]) [(set_attr "predicable" "no")])
(define_split (define_split
[(set (match_operand 0 "destination_operand" "") [(set (match_operand 0 "not_postinc_destination_operand" "")
(if_then_else (if_then_else
(match_operator 4 "predicate_operator" (match_operator 4 "predicate_operator"
[(match_operand:BI 1 "register_operand" "") [(match_operand:BI 1 "register_operand" "")
(const_int 0)]) (const_int 0)])
(match_operand 2 "move_operand" "") (match_operand 2 "not_postinc_move_operand" "")
(match_operand 3 "move_operand" "")))] (match_operand 3 "not_postinc_move_operand" "")))]
"reload_completed" "reload_completed"
[(const_int 0)] [(const_int 0)]
{ {
...@@ -4188,14 +4188,15 @@ ...@@ -4188,14 +4188,15 @@
;; ;;
(define_insn "*cmovsi_internal" (define_insn "*cmovsi_internal"
[(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") [(set (match_operand:SI 0 "not_postinc_destination_operand"
"=r,m,*f,r,m,*f,r,m,*f")
(if_then_else:SI (if_then_else:SI
(match_operator 4 "predicate_operator" (match_operator 4 "predicate_operator"
[(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
(const_int 0)]) (const_int 0)])
(match_operand:SI 2 "move_operand" (match_operand:SI 2 "not_postinc_move_operand"
"0,0,0,rim*f,rO,rO,rim*f,rO,rO") "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
(match_operand:SI 3 "move_operand" (match_operand:SI 3 "not_postinc_move_operand"
"rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
"ia64_move_ok (operands[0], operands[2]) "ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])" && ia64_move_ok (operands[0], operands[3])"
......
gcc/config/ia64/predicates.md
...@@ -281,6 +281,12 @@ ...@@ -281,6 +281,12 @@
|| GET_CODE (XEXP (op, 0)) != POST_MODIFY || GET_CODE (XEXP (op, 0)) != POST_MODIFY
|| GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) != REG"))) || GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) != REG")))
;; Like destination_operand, but don't allow any post-increments.
(define_predicate "not_postinc_destination_operand"
(and (match_operand 0 "nonimmediate_operand")
(match_test "GET_CODE (op) != MEM
|| GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
;; Like memory_operand, but don't allow post-increments. ;; Like memory_operand, but don't allow post-increments.
(define_predicate "not_postinc_memory_operand" (define_predicate "not_postinc_memory_operand"
(and (match_operand 0 "memory_operand") (and (match_operand 0 "memory_operand")
...@@ -332,6 +338,12 @@ ...@@ -332,6 +338,12 @@
} }
}) })
;; Like move_operand but don't allow post-increments.
(define_predicate "not_postinc_move_operand"
(and (match_operand 0 "move_operand")
(match_test "GET_CODE (op) != MEM
|| GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
;; True if OP is a register operand that is (or could be) a GR reg. ;; True if OP is a register operand that is (or could be) a GR reg.
(define_predicate "gr_register_operand" (define_predicate "gr_register_operand"
(match_operand 0 "register_operand") (match_operand 0 "register_operand")
......
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