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Commit cca18f3b by Claudiu Zissulescu Committed by Claudiu Zissulescu
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[ARC] Cleanup sign/zero extend patterns 

Clean up sign/zero extend patterns.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (zero_extendqihi2_i): Cleanup pattern.
	(zero_extendqisi2_ac): Likewise.
	(zero_extendhisi2_i): Likewise.
	(extendqihi2_i): Likewise.
	(extendqisi2_ac): Likewise.
	(extendhisi2_i): Likewise.

From-SVN: r277883
parent 06af1f1a
Showing with 65 additions and 49 deletions
gcc/ChangeLog
2019-11-06 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (zero_extendqihi2_i): Cleanup pattern.
(zero_extendqisi2_ac): Likewise.
(zero_extendhisi2_i): Likewise.
(extendqihi2_i): Likewise.
(extendqisi2_ac): Likewise.
(extendhisi2_i): Likewise.
2019-11-06 Richard Biener <rguenther@suse.de> 2019-11-06 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (vectorizable_reduction): Remember reduction * tree-vect-loop.c (vectorizable_reduction): Remember reduction
gcc/config/arc/arc.md
...@@ -1801,18 +1801,22 @@ core_3, archs4x, archs4xd, archs4xd_slow" ...@@ -1801,18 +1801,22 @@ core_3, archs4x, archs4xd, archs4xd_slow"
[(set_attr "type" "cmove,cmove") [(set_attr "type" "cmove,cmove")
(set_attr "length" "8,16")]) (set_attr "length" "8,16")])
;; -------------------------------------------------------------------
;; Sign/Zero extension
;; -------------------------------------------------------------------
(define_insn "*zero_extendqihi2_i" (define_insn "*zero_extendqihi2_i"
[(set (match_operand:HI 0 "dest_reg_operand" "=Rcq,Rcq#q,Rcw,w,r,r") [(set (match_operand:HI 0 "dest_reg_operand" "=q,q,r,r,r,r")
(zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "0,Rcq#q,0,c,Ucm,m")))] (zero_extend:HI
(match_operand:QI 1 "nonvol_nonimm_operand" "0,q,0,r,Ucm,m")))]
"" ""
"@ "@
extb%? %0,%1%& extb%?\\t%0,%1
extb%? %0,%1%& extb%?\\t%0,%1
bmsk%? %0,%1,7 bmsk%?\\t%0,%1,7
extb %0,%1 extb\\t%0,%1
xldb%U1 %0,%1 xldb%U1\\t%0,%1
ldb%U1 %0,%1" ldb%U1\\t%0,%1"
[(set_attr "type" "unary,unary,unary,unary,load,load") [(set_attr "type" "unary,unary,unary,unary,load,load")
(set_attr "iscompact" "maybe,true,false,false,false,false") (set_attr "iscompact" "maybe,true,false,false,false,false")
(set_attr "predicable" "no,no,yes,no,no,no")]) (set_attr "predicable" "no,no,yes,no,no,no")])
...@@ -1825,18 +1829,19 @@ core_3, archs4x, archs4xd, archs4xd_slow" ...@@ -1825,18 +1829,19 @@ core_3, archs4x, archs4xd, archs4xd_slow"
) )
(define_insn "*zero_extendqisi2_ac" (define_insn "*zero_extendqisi2_ac"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcq#q,Rcw,w,qRcq,!*x,r,r") [(set (match_operand:SI 0 "dest_reg_operand" "=q,q,r,r,q,!*x,r,r")
(zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "0,Rcq#q,0,c,T,Usd,Ucm,m")))] (zero_extend:SI
(match_operand:QI 1 "nonvol_nonimm_operand" "0,q,0,r,T,Usd,Ucm,m")))]
"" ""
"@ "@
extb%? %0,%1%& extb%?\\t%0,%1
extb%? %0,%1%& extb%?\\t%0,%1
bmsk%? %0,%1,7 bmsk%?\\t%0,%1,7
extb %0,%1 extb\\t%0,%1
ldb%? %0,%1%& ldb%?\\t%0,%1
ldb%? %0,%1%& ldb%?\\t%0,%1
xldb%U1 %0,%1 xldb%U1\\t%0,%1
ldb%U1 %0,%1" ldb%U1\\t%0,%1"
[(set_attr "type" "unary,unary,unary,unary,load,load,load,load") [(set_attr "type" "unary,unary,unary,unary,load,load,load,load")
(set_attr "iscompact" "maybe,true,false,false,true,true,false,false") (set_attr "iscompact" "maybe,true,false,false,true,true,false,false")
(set_attr "predicable" "no,no,yes,no,no,no,no,no")]) (set_attr "predicable" "no,no,yes,no,no,no,no,no")])
...@@ -1849,23 +1854,23 @@ core_3, archs4x, archs4xd, archs4xd_slow" ...@@ -1849,23 +1854,23 @@ core_3, archs4x, archs4xd, archs4xd_slow"
) )
(define_insn "*zero_extendhisi2_i" (define_insn "*zero_extendhisi2_i"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,q,Rcw,w,!x,Rcqq,r,r") [(set (match_operand:SI 0 "dest_reg_operand" "=q,q,r,r,!x,q,r,r")
(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,c,Usd,T,Ucm,m")))] (zero_extend:SI
(match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,r,Usd,T,Ucm,m")))]
"" ""
"@ "@
ext%_%? %0,%1%& ext%_%?\\t%0,%1
ext%_%? %0,%1%& ext%_%?\\t%0,%1
bmsk%? %0,%1,15 bmsk%?\\t%0,%1,15
ext%_ %0,%1 ext%_\\t%0,%1
ld%_%? %0,%1 ld%_%?\\t%0,%1
ld%_%? %0,%1 ld%_%?\\t%0,%1
* return TARGET_EM ? \"xldh%U1%V1 %0,%1\" : \"xldw%U1 %0,%1\"; xldw%U1\\t%0,%1
ld%_%U1%V1 %0,%1" ld%_%U1%V1\\t%0,%1"
[(set_attr "type" "unary,unary,unary,unary,load,load,load,load") [(set_attr "type" "unary,unary,unary,unary,load,load,load,load")
(set_attr "iscompact" "maybe,true,false,false,true,true,false,false") (set_attr "iscompact" "maybe,true,false,false,true,true,false,false")
(set_attr "predicable" "no,no,yes,no,no,no,no,no")]) (set_attr "predicable" "no,no,yes,no,no,no,no,no")])
(define_expand "zero_extendhisi2" (define_expand "zero_extendhisi2"
[(set (match_operand:SI 0 "dest_reg_operand" "") [(set (match_operand:SI 0 "dest_reg_operand" "")
(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))] (zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))]
...@@ -1876,19 +1881,19 @@ core_3, archs4x, archs4xd, archs4xd_slow" ...@@ -1876,19 +1881,19 @@ core_3, archs4x, archs4xd, archs4xd_slow"
;; Sign extension instructions. ;; Sign extension instructions.
(define_insn "*extendqihi2_i" (define_insn "*extendqihi2_i"
[(set (match_operand:HI 0 "dest_reg_operand" "=Rcqq,r,r,r") [(set (match_operand:HI 0 "dest_reg_operand" "=q,r,r,r")
(sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "Rcqq,r,Uex,m")))] (sign_extend:HI
(match_operand:QI 1 "nonvol_nonimm_operand" "q,r,Uex,m")))]
"" ""
"@ "@
sexb%? %0,%1%& sexb%?\\t%0,%1
sexb %0,%1 sexb\\t%0,%1
ldb.x%U1 %0,%1 ldb.x%U1\\t%0,%1
ldb.x%U1 %0,%1" ldb.x%U1\\t%0,%1"
[(set_attr "type" "unary,unary,load,load") [(set_attr "type" "unary,unary,load,load")
(set_attr "iscompact" "true,false,false,false") (set_attr "iscompact" "true,false,false,false")
(set_attr "length" "*,*,*,8")]) (set_attr "length" "*,*,*,8")])
(define_expand "extendqihi2" (define_expand "extendqihi2"
[(set (match_operand:HI 0 "dest_reg_operand" "") [(set (match_operand:HI 0 "dest_reg_operand" "")
(sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))] (sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))]
...@@ -1897,14 +1902,15 @@ core_3, archs4x, archs4xd, archs4xd_slow" ...@@ -1897,14 +1902,15 @@ core_3, archs4x, archs4xd, archs4xd_slow"
) )
(define_insn "*extendqisi2_ac" (define_insn "*extendqisi2_ac"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,r,r") [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r,r")
(sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "Rcqq,c,Uex,m")))] (sign_extend:SI
(match_operand:QI 1 "nonvol_nonimm_operand" "q,r,Uex,m")))]
"" ""
"@ "@
sexb%? %0,%1%& sexb%?\\t%0,%1
sexb %0,%1 sexb\\t%0,%1
ldb.x%U1 %0,%1 ldb.x%U1\\t%0,%1
ldb.x%U1 %0,%1" ldb.x%U1\\t%0,%1"
[(set_attr "type" "unary,unary,load,load") [(set_attr "type" "unary,unary,load,load")
(set_attr "iscompact" "true,false,false,false") (set_attr "iscompact" "true,false,false,false")
(set_attr "length" "*,*,*,8")]) (set_attr "length" "*,*,*,8")])
...@@ -1917,15 +1923,16 @@ core_3, archs4x, archs4xd, archs4xd_slow" ...@@ -1917,15 +1923,16 @@ core_3, archs4x, archs4xd, archs4xd_slow"
) )
(define_insn "*extendhisi2_i" (define_insn "*extendhisi2_i"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,Rcqq,r,r") [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,q,r,r")
(sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "Rcqq,c,Ucd,Uex,m")))] (sign_extend:SI
(match_operand:HI 1 "nonvol_nonimm_operand" "q,r,Ucd,Uex,m")))]
"" ""
"@ "@
sex%_%? %0,%1%& sex%_%?\\t%0,%1
sex%_ %0,%1 sex%_\\t%0,%1
ldh%?.x %0,%1%& ldh%?.x\\t%0,%1%&
ld%_.x%U1%V1 %0,%1 ld%_.x%U1%V1\\t%0,%1
ld%_.x%U1%V1 %0,%1" ld%_.x%U1%V1\\t%0,%1"
[(set_attr "type" "unary,unary,load,load,load") [(set_attr "type" "unary,unary,load,load,load")
(set_attr "iscompact" "true,false,true,false,false") (set_attr "iscompact" "true,false,true,false,false")
(set_attr "length" "*,*,*,4,8")]) (set_attr "length" "*,*,*,4,8")])
......
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